JAJSKM1C october   2019  – september 2021 UCC5870-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Electrical Characteristics
    8. 6.8  SPI Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Supplies
        1. 7.3.1.1 VCC1
        2. 7.3.1.2 VCC2
        3. 7.3.1.3 VEE2
        4. 7.3.1.4 VREG1
        5. 7.3.1.5 VREG2
        6. 7.3.1.6 VREF
        7. 7.3.1.7 Other Internal Rails
      2. 7.3.2 Driver Stage
      3. 7.3.3 Integrated ADC for Front-End Analog (FEA) Signal Processing
        1. 7.3.3.1 AI* Setup
        2. 7.3.3.2 ADC Setup and Sampling Modes
          1. 7.3.3.2.1 Center Sampling Mode
          2. 7.3.3.2.2 Edge Sampling Mode
          3. 7.3.3.2.3 Hybrid Mode
        3. 7.3.3.3 DOUT Functionality
      4. 7.3.4 Fault and Warning Classification
      5. 7.3.5 Diagnostic Features
        1. 7.3.5.1  Undervoltage Lockout (UVLO) and Overvoltage Lockout (OVLO)
          1. 7.3.5.1.1 Built-In Self Test (BIST)
            1. 7.3.5.1.1.1 Analog Built-In Self Test (ABIST)
            2. 7.3.5.1.1.2 Function BIST
            3. 7.3.5.1.1.3 Clock Monitor
              1. 7.3.5.1.1.3.1 Clock Monitor Built-In Self Test
        2. 7.3.5.2  CLAMP, OUTH, and OUTL Clamping Circuits
        3. 7.3.5.3  Active Miller Clamp
        4. 7.3.5.4  DESAT based Short Circuit Protection (DESAT)
        5. 7.3.5.5  Shunt Resistor based Overcurrent Protection (OCP) and Short Circuit Protection (SCP)
        6. 7.3.5.6  Temperature Monitoring and Protection for the Power Transistors
        7. 7.3.5.7  Active High Voltage Clamping (VCECLP)
        8. 7.3.5.8  Two-Level Turn-Off
        9. 7.3.5.9  Soft Turn-Off (STO)
        10. 7.3.5.10 Thermal Shutdown (TSD) and Temperature Warning (TWN) of Driver IC
        11. 7.3.5.11 Active Short Circuit Support (ASC)
        12. 7.3.5.12 Shoot-Through Protection (STP)
        13. 7.3.5.13 Gate Voltage Monitoring and Status Feedback
        14. 7.3.5.14 VGTH Monitor
        15. 7.3.5.15 Cyclic Redundancy Check (CRC)
          1. 7.3.5.15.1 Calculating CRC
        16. 7.3.5.16 Configuration Data CRC
        17. 7.3.5.17 SPI Transfer Write/Read CRC
          1. 7.3.5.17.1 SDI CRC Check
          2. 7.3.5.17.2 SDO CRC Check
        18. 7.3.5.18 TRIM CRC Check
    4. 7.4 Device Functional Modes
      1. 7.4.1 State 1: RESET
      2. 7.4.2 State 2: Configuration 1
      3. 7.4.3 State 3: Configuration 2
      4. 7.4.4 State 4: Active
    5. 7.5 Programming
      1. 7.5.1 SPI Communication
        1. 7.5.1.1 System Configuration of SPI Communication
          1. 7.5.1.1.1 Independent Slave Configuration
          2. 7.5.1.1.2 Daisy Chain Configuration
          3. 7.5.1.1.3 Address-based Configuration
        2. 7.5.1.2 SPI Data Frame
          1. 7.5.1.2.1 Writing a Register
          2. 7.5.1.2.2 Reading a Register
    6. 7.6 Register Maps
      1. 7.6.1 UCC5870 Registers
  9. 8 Applications and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Power Dissipation Considerations
      2. 8.1.2 Device Addressing
    2. 8.2 Typical Application Using Internal ADC Reference and Power FET Sense Current Monitoring
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VCC1, VCC2, and VEE2 Bypass Capacitors
        2. 8.2.2.2 VREF, VREG1, and VREG2 Bypass Capacitors
        3. 8.2.2.3 Bootstrap Capacitor (VBST)
        4. 8.2.2.4 VCECLP Input
        5. 8.2.2.5 External CLAMP Output
        6. 8.2.2.6 AI* Inputs
        7. 8.2.2.7 OUTH/ OUTL Outputs
        8. 8.2.2.8 nFLT* Outputs
      3. 8.2.3 Application Curves
    3. 8.3 Typical Application Using DESAT Power FET Monitoring
      1. 8.3.1 Detailed Design Procedure
        1. 8.3.1.1 DESAT Input
      2. 8.3.2 Application Curves
  10. 9 Power Supply Recommendations
    1. 9.1 VCC1 Power Supply
    2. 9.2 VCC2 Power Supply
    3. 9.3 VEE2 Power Supply
    4. 9.4 VREF Supply (Optional)
  11. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Component Placement
      2. 10.1.2 Grounding Considerations
      3. 10.1.3 High-Voltage Considerations
      4. 10.1.4 Thermal Considerations
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.7 Electrical Characteristics

Over recommended operating conditions unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VIT+(UVLO1)  UVLO threshold of VCC1 rising  UVOV1_LEVEL = 0 2.6 2.75 2.9 V
VIT+(UVLO1) UVLO threshold of VCC1 rising UVOV1_LEVEL = 1 4.5 4.65 4.8 V
VIT- (UVLO1) UVLO threshold of VCC1 falling UVOV1_LEVEL = 0 2.3 2.45 2.6 V
VIT- (UVLO1) UVLO threshold of VCC1 falling UVOV1_LEVEL = 1 4.2 4.35 4.5 V
VHYS (UVLO1) UVLO threshold hysteresis of VCC1 0.30 V
tUVLO1 VCC1 UVLO detection deglitch time 20 µs
VIT-(OVLO1)  OVLO threshold of VCC1 falling  UVOV1_LEVEL = 0 3.7 3.85 4.0 V
VIT-(OVLO1)  OVLO threshold of VCC1 falling UVOV1_LEVEL = 1 5.2 5.35 5.5 V
VIT+(OVLO1) OVLO threshold of VCC1 rising UVOV1_LEVEL = 0 4.0 4.15 4.3 V
VIT+ (OVLO1) OVLO threshold of VCC1 rising UVOV1_LEVEL = 1 5.5 5.65 5.8 V
VHYS (OVLO1) OVLO threshold hysteresis of VCC1 0.30 V
tOVLO1 VCC1 OVLO detection deglitch time 20 µs
VIT+(UVLO2)   UVLO threshold voltage of VCC2  rising with reference to GND2  UVLO2TH = 00b 15.2 16 16.8 V
UVLO2TH = 01b 13.3 14 14.7 V
UVLO2TH = 10b 11.4 12 12.6 V
UVLO2TH = 11b 9.5 10 10.5 V
VIT- (UVLO2) UVLO threshold voltage of VCC2  falling with reference to GND2 UVLO2TH = 00b 14.25 15 15.75 V
UVLO2TH = 01b 12.35 13 13.65 V
UVLO2TH = 10b 10.45 11 11.55 V
UVLO2TH = 11b 8.55 9 9.45 V
VHYS (UVLO2) UVLO threshold voltage hysteresis of VCC2 1 V
tUVLO2 VCC2 UVLO detection deglitch time 20 µs
VIT-(OVLO2)  OVLO threshold voltage of VCC2  falling  with reference to GND2  OVLO2TH = 00b 21.85 23 24.15 V
OVLO2TH = 01b 19.95 21 22.05 V
OVLO2TH = 10b 18.05 19 19.95 V
OVLO2TH = 11b 16.15 17 17.85 V
VIT+ (OVLO2) OVLO threshold voltage of VCC2  rising  with reference to GND2 OVLO2TH = 00b 22.8 24 25.2 V
OVLO2TH = 01b 20.9 22 23.1 V
OVLO2TH = 10b 19 20 21 V
OVLO2TH = 11b 17.1 18 18.9 V
VHYS (OVLO2) OVLO threshold voltage hysteresis of VCC2 1 V
tOVLO2 VCC2 OVLO detection blanking time 20 µs
VIT-(UVLO3)  UVLO threshold voltage of VEE2 falling  with reference to GND2  UVLO3TH = 00b –3.15 –3 –2.85 V
UVLO3TH = 01b –5.25 –5 –4.75 V
UVLO3TH = 10b –8.4 –8 –7.6 V
UVLO3TH = 11b –10.5 –10 –9.5 V
VIT+ (UVLO3) UVLO threshold voltage of VEE2 rising  with reference to GND2 UVLO3TH = 00b –2.1 –2 –1.9 V
UVLO3TH = 01b –4.2 –4 –3.8 V
UVLO3TH = 10b –7.35 –7 –6.65 V
UVLO3TH = 11b –9.45 –9 –8.55 V
VHYS (UVLO3) UVLO threshold voltage hysteresis of VEE2 1 V
tUVLO3 VEE2 UVLO detection blanking time 20 µs
VIT+(OVLO3) OVLO threshold voltage of VEE2 rising with reference to GND2 OVLO3TH = 00b –5.25 –5 –4.75 V
OVLO3TH = 01b –7.35 –7 –6.65 V
OVLO3TH = 10b –10.5 –10 –9.5 V
OVLO3TH = 11b –12.6 –12 –11.4 V
VIT-(OVLO3) OVLO threshold voltage of VEE2 falling with reference to GND2 OVLO3TH = 00b –6.3 –6 –5.7 V
OVLO3TH = 01b –8.4 –8 –7.6 V
OVLO3TH = 10b –11.55 –11 –10.45 V
OVLO3TH = 11b –13.65 –13 –12.35 V
VHYS(OVLO3) OVLO threshold voltage hysteresis of VEE2 1 V
tOVLO3 VEE2 OVLO detection blanking time 20 µs
IQVCC1 Quiescent Current of VCC1 No switching, VCC1 = 5V 7.7 mA
IQVCC2 Quiescent Current of VCC2 No switching, VCC2 = 20V, VEE2 = -10V 15 mA
IQVEE2 Quiescent Current of VEE2 No switching, VCC2 = 20V, VEE2 = -10V 15 mA
tRP(VCC1) Slew rate of VCC1 0.1 V/µs
tRP(VCC2) Slew rate of VCC2 0.1 V/µs
tRP(VEE2) Slew rate of VEE2 0.1 V/µs
LOGIC IO
VIH Input-high threshold voltage of primary IO (IN+, IN-, ASC, and ASC_EN) Input rising, VCC1 = 3.3V 0.7*VCC1 V
Input-high threshold voltage of secondary IO in ASC mode (AI5, and AI6) Input rising, VREF=4V 3.0 V
VIL Input-low threshold voltage of primary IO (IN+, IN-, ASC, and ASC_EN) VCC1 = 3.3V 0.3*VCC1 V
Input-low input-threshold voltage of secondary IO in ASC mode (AI5 and AI6) Input falling 1.5 V
VHYS(IN) Input hysteresis voltage of primary IO (IN+, IN-, ASC,  and ASC_EN) VCC1=3.3V 0.1*VCC1 V
Input hysteresis voltage of secondary IO in ASC mode (AI5, and AI6) 0.5 V
ILI Leakage current on the input IO pins ASC, ASC_EN, IN+, IN-, CLK, and SDI VIO = GND1, VIO is the voltage on IO pins 5 µA
Leakage current on nCS VIO = VCC1, VIO is the voltage on IO pins 5 µA
RPUI Pullup resistance for nCS 40 100 kΩ
RPDI Pulldown resistance for ASC, ASC_EN, IN+, IN-, CLK, and SDI 40 100 kΩ
Pulldown resistance for AI5 and AI6 in ASC mode 800 1200 kΩ
VOH Output logic-high voltage (SDO) 4.5mA output current, VCC1 = 5V  0.9*VCC1 V
VOL Output logic-low voltage (nFLT1, nFLT2, and SDO) 4.5mA sink current, VCC1 = 5V  0.1*VCC1 V
fDOUT Output frequency of DOUT pin FREQ_DOUT = 00b 13.9 kHz
FREQ_DOUT = 01b 27.8 kHz
FREQ_DOUT = 10b 55.7 kHz
FREQ_DOUT = 11b 111.4 kHz
DDOUT Duty of DOUT VAI* = 0.36 V 10 %
VAI* = 1.8 V 50 %
VAI* = 3.24 V 90 %
ILO Leakage current on pin nFLT* nFLT* = HiZ, VCC1 on nFLT* pin –5 5 µA
Leakage current on pin SDO nCS = 1 –5 5 µA
RPUO Pullup resistance for pin nFLT* 40 100 kΩ
DRIVER STAGE
VOUTH High-level output voltage (OUT and OUTH) IOUT = -100 mA VCC2 – 0.033 V
VOUTL Low-level output voltage (OUT and OUTL) IOUT = 100 mA 33 mV
IOUTH Gate driver high output current IN+= high, IN- = low, VCC2 - VOUTH = 5 V 15 A
IOUTL Gate driver low output current IN- = low, IN + = high, VOUTL - VEE2 = 5 V 15 A
ISTO Driver low output current during SC and OC faults VOUTL - VEE2 = 6 V  and STO_CURR = 00b, 100℃ to 150℃ 0.24 0.3 0.36 A
VOUTL - VEE2 = 6 V and STO_CURR = 01b, 100℃ to 150℃ 0.48 0.6 0.72 A
VOUTL - VEE2 = 6 V and STO_CURR = 10b, 100℃ to 150℃ 0.72 0.9 1.08 A
VOUTL - VEE2 = 6 V and STO_CURR = 11b, 100℃ to 150℃ 0.96 1.2 1.44 A
ACTIVE MILLER CLAMP
VCLP Low-level clamp voltage (internal Miller clamp) ICLP = 100 mA 100 mV
Miller clamp current MCLPTH=11b, VCLAMP = VEE2+4 V 3.2 A
VCLPTH Clamp threshold voltage with reference to VEE2 MCLPTH = 00b 1.2 1.5 1.8 V
MCLPTH = 01b 1.6 2 2.5 V
MCLPTH = 10b 2.25 3 3.75 V
MCLPTH = 11b 3 4 5 V
VECLP CLAMP output voltage in external Miller clamp mode 4.5 5 5.5 V
RECLP_PD CLAMP pulldown resistance in external Miller clamp mode 13 Ω
RECLP_PU CLAMP pull-up resistance in external Miller clamp mode 13 Ω
SHORT CIRCUIT CLAMPING
VCLP-OUT Clamping voltage (VOUTH - VCC2, VCLAMP - VCC2) IN+= high, IN- = low, tCLP = 10us, IOUTH or ICLAMP = 500 mA 0.8 1.6 V
ACTIVE PULLDOWN
VOUTSD Active shut-down voltage on OUTL IOUTL = 30mA, VCC2 = open     1.55 V
VOUTSD Active shut-down voltage on OUTL  IOUTL = 0.1xIOUTL, VCC2 = open 2.5 V
DESAT SHORT-CIRCUIT PROTECTION
VDESATth DESAT detection threshold voltage wrt GND2 DESATTH = 0000b 2.25 2.5 2.75 V
DESATTH = 0001b 2.7 3 3.3 V
DESATTH = 0010b 3.15 3.5 3.85 V
DESATTH = 0011b 3.6 4 4.4 V
DESATTH = 0100b 4.05 4.5 4.95 V
DESATTH = 0101b 4.5 5 5.5 V
DESATTH = 0110b 4.95 5.5 6.05 V
DESATTH = 0111b 5.4 6 6.6 V
DESATTH = 1000b 5.85 6.5 7.15 V
DESATTH = 1001b 6.3 7 7.7 V
DESATTH = 1010b 6.75 7.5 8.25 V
DESATTH = 1011b 7.2 8 8.8 V
DESATTH = 1100b 7.65 8.5 9.35 V
DESATTH = 1101b 8.1 9 9.9 V
DESATTH = 1110b 8.55 9.5 10.45 V
DESATTH = 1111b 9 10 11 V
VDESATL DESAT voltage with respect to GND2 when OUTL is driven low 1 V
ICHG Blanking capacitor charging current V(DESAT) - GND2 = 2 V, DESAT_CHG_CURR = 00b 0.555 0.6 0.645 mA
V(DESAT) - GND2 = 2 V, DESAT_CHG_CURR = 01b 0.6475 0.7 0.7525 mA
V(DESAT) - GND2 = 2 V, DESAT_CHG_CURR = 10b 0.74 0.8 0.86 mA
V(DESAT) - GND2 = 2 V, DESAT_CHG_CURR = 11b 0.925 1 1.075 mA
IDCHG Blanking capacitor discharging current V(DESAT) - GND2 = 6 V 14 mA
tLEB DESAT leading edge blanking time 127  158 250  ns
tDESFLT DESAT pin glitch filter DESAT_DEGLITCH=0  90 158 190 ns
tDESFLT DESAT pin glitch filter DESAT_DEGLITCH=1 270 316 401 ns
tDESAT (90%) DESAT protection reaction time from event to action (includes deglitch time) VDESAT>VDESATth to VOUTL 90% of VCC2, CLOAD = 1 nF, DESAT_DEGLITCH=0 160 + tDESFLT   ns
OVERCURRENT PROTECTION
VOCth Over current detection threshold voltage OCTH = 0000b 170  200 225  mV
OCTH = 0001b 220  250 275  mV
OCTH = 0010b 270 
300		 330  mV
OCTH = 0011b 315 
350		 375  mV
OCTH = 0100b 360 
400		 440  mV
OCTH = 0101b 410 
450		 475  mV
OCTH = 0110b 460 
500		 525  mV
OCTH = 0111b 520  550 575  mV
OCTH = 1000b 570  600 630  mV
OCTH = 1001b 610  650 690  mV
OCTH = 1010b 660  700 740  mV
OCTH = 1011b 710  750 790  mV
OCTH = 1100b 760  800 840  mV
OCTH = 1101b 807  850 893  mV
OCTH = 1110b 855  900 945  mV
OCTH = 1111b 902 950 998  mV
VSCth Short circuit protection threshold SCTH = 00b 460 500 530 mV
SCTH = 01b 700 750 785 mV
SCTH = 10b 945 1000 1050 mV
SCTH = 11b 1185 1250 1312 mV
tSCBLK Short circuit protection blanking time with reference to system clock SC_BLK = 00b 100 ns
SC_BLK = 01b 200 ns
SC_BLK = 10b 400 ns
SC_BLK = 11b 800 ns
tOCBLK Over current protection blanking time with reference to system clock OC_BLK = 000b 500 ns
OC_BLK = 001b 1000 ns
OC_BLK = 010b 1500 ns
OC_BLK = 011b 2000 ns
OC_BLK = 100b 2500 ns
OC_BLK = 101b 3000 ns
OC_BLK = 110b 5000 ns
OC_BLK = 111b 10000 ns
tSCFLT Short circuit protection deglitch filter 50 150 200 ns
tOCFLT Over current protection deglitch filter 50 150 200 ns
tSC(90%) Short circuit protection reaction time from event to action (includes deglitch time) VAIx > VSCth to VOUTL at 90% of VCC2, CLOAD = 1nF, tSCBLK expired 175 + tSCFLT ns
tOC(90%) Over current protection reaction time from event to action (includes deglitch time) VAIx > VOCth to VOUTL at 90% of VCC2, CLOAD = 1nF, tOCBLK expired 175 + tOCFLT ns
TWO-LEVEL TURN-OFF PLATEAU VOLTAGE LEVEL
V2 LOFF Plateau voltage (w.r.t. GND2) during two-level turnoff 2LOFF_VOLT = 000b 5 6 7 V
2LOFF_VOLT = 001b 6 7 8 V
2LOFF_VOLT = 010b 7 8 9 V
2LOFF_VOLT = 011b 8 9 10 V
2LOFF_VOLT = 100b 9 10 11 V
2LOFF_VOLT = 101b 10 11 12 V
2LOFF_VOLT = 110b 11 12 13 V
2LOFF_VOLT = 111b 12 13 14 V
t2 LOFF Plateau voltage during two-level turnoff hold time 2LOFF_TIME = 000b 150 ns
2LOFF_TIME = 001b 300 ns
2LOFF_TIME = 010b 450 ns
2LOFF_TIME = 011b 600 ns
2LOFF_TIME = 100b 1000 ns
2LOFF_TIME = 101b 1500 ns
2LOFF_TIME = 110b 2000 ns
2LOFF_TIME = 111b 2500 ns
I2 LOFF Discharge current for transition to plateau voltage level 2LOFF_CURR = 00b, 100℃ to 150℃ 0.24 0.3 0.36 A
2LOFF_CURR = 01b, 100℃ to 150℃ 0.48 0.6 0.72 A
2LOFF_CURR = 10b, 100℃ to 150℃ 0.72 0.9 1.08 A
2LOFF_CURR = 11b, 100℃ to 150℃ 0.96 1.2 1.44 A
HIGH VOLTAGE CLAMPING
VCECLPTH VCE clamping threshold with respect to VEE2 1.5 2.2 2.9 V
VCECLPHYS VCE clamping threshold hysteresis 200 mV
tVCECLP VCE clamping intervention-time 30  ns
tVCECLP_HLD VCE clamping hold on time VCE_CLMP_HLD_TIME = 00b 100 ns
VCE_CLMP_HLD_TIME = 01b 200 ns
VCE_CLMP_HLD_TIME = 10b 300 ns
VCE_CLMP_HLD_TIME = 11b 400 ns
OVERTEMPERATURE PROTECTION
TSD_SET Overtemperature protection set for driver 155 °C
TSD_CLR Overtemperature protection clear for driver 135 °C
TWN_SET Overtemperature warning set for driver 130 °C
TWN_CLR Overtemperature warning clear for driver 110 °C
THYS Hysteresis for thermal comparators 20 °C
ITO Bias current for temp sensing diode for pins AI1, AI3, and AI5 TEMP_CURR = 00b, Tj = 100C to 150C 0.097 0.1 0.103 mA
TEMP_CURR = 01b, Tj = 100C to 150C 0.291 0.3 0.309 mA
TEMP_CURR = 10b, Tj = 100C to 150C 0.582  0.6  0.618  mA
TEMP_CURR = 11b, Tj = 100C to 150C 0.97 1 1.03 mA
VPS_TSDth The threshold of power switch over temperature protection. TSDTH_PS = 000b 0.95 1 1.05 V
TSDTH_PS = 001b 1.1875 1.25 1.3125 V
TSDTH_PS = 010b 1.425 1.5 1.575 V
TSDTH_PS = 011b 1.6625 1.75 1.8375 V
TSDTH_PS = 100b 1.9 2 2.1 V
TSDTH_PS = 101b 2.1375 2.25 2.3625 V
TSDTH_PS = 110b 2.375 2.5 2.625 V
TSDTH_PS = 111b 2.6125 2.75 2.8875 V
tPS_TSDFLT Power switch thermal shutdown deglitch time PS_TSD_DEGLITCH = 00b 250 ns
PS_TSD_DEGLITCH = 01b 500 ns
PS_TSD_DEGLITCH = 10b 750 ns
PS_TSD_DEGLITCH = 11b 1000 ns
GATE VOLTAGE MONITOR
VGMH Gate monitor threshold value with reference to VCC2 IN+= high and IN- = low – 4 – 3 – 2 V
VGML Gate monitor threshold value with reference to VEE2 IN + = low and IN- = high 2 3 4 V
tGMBLK Gate voltage monitor blanking time after driver receives PWM transition  GM_BLK = 00b 500 ns
GM_BLK = 01b 1000 ns
GM_BLK = 10b 2500  ns
GM_BLK = 11b 4000 ns
tGMFLT Gate voltage monitor deglitch time  250 ns
IVGTHM Charge current for VGTH measurement VCC2 - VOUTH = 10V 2 mA
tdVGTHM Delay time between VGTH measurement control command to gate voltage sampling point.   2300   µs
ADC
FSR Full scale input voltage range for A1 to A6 0 3.6 3.636 V
VREF Required voltage for external VREF Accuracy of external reference directly affects the accuracy of the ADC 4 V
Internal VREF output voltage 4 V
INL Integral non-linearity External reference, VREF = 4V -1.2 1.2 LSB
Internal reference  -4 9 LSB
DNL Differential non-linearity External reference, VREF = 4V -0.75 0.75 LSB
Internal reference  -0.75 0.75 LSB
tADREFEXT External ADC reference turn on delay time from VCC2 > VIT-(UVLO2)  VIT-(UVLO2) to 10% of VREF 10 µs
ITO2 Pull up current on AI2,4,6 pins VAI2,4,6= VREF/2, ITO2_EN=H 10 15 µA
thybrid IN+ hold time to cause switchover between center mode and edge mode   ADC in hybrid mode configuration 0.4 ms
tCONV Time to complete ADC conversion   5.1 µs
tRR Time between ADC conversions in Edge mode   ADC in edge mode or hybrid mode (after tHYBRID) configuration 7.5 µs