JAJSPD9 December   2022 UCC5871-Q1

PRODUCTION DATA  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  SPI Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Component Placement
      2. 7.1.2 Grounding Considerations
      3. 7.1.3 High-Voltage Considerations
      4. 7.1.4 Thermal Considerations
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5 Pin Configuration and Functions

GUID-20200608-SS0I-DXF0-DG42-K3WDGW44HGXK-low.gif Figure 5-1 DWJ36-Pin SOICTop View
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NO. NAME
1 GND1 G Primary Side Ground. Connect all GND1 pins together and to the PCB ground plane on the primary side.
2 NC — No internal connection. Connect to GND1.
3 NC — No internal connection. Connect to GND1.
4 NC — No internal connection. Connect to GND1.
5 NC — No internal connection. Connect to GND1.
6 ASC_EN I Active Short Circuit Enable Input. ASC_EN enables the ASC function and forces the output of the driver to the state defined by the ASC input. If ASC is high, OUTH is pulled high. If ASC is low, OUTL is pulled low.
7 nFLT1 O Fault Indicator Output 1. nFLT1 is used to interrupt the host when a fault occurs. Faults that are unmasked pull nFLT1 low when the fault occurs. nFLT1 is high when all faults are either non-existent or masked.
8 nFLT2/DOUT O Fault Indicator Output 2. nFLT2 is used to interrupt the host when a fault occurs. Additionally, nFLT2 may be configured as DOUT to provide the host controller a PWM signal with a duty cycle relative to the ADC input of interest. Faults that are unmasked pull nFLT2 low when the fault occurs. nFLT2 is high when all faults are either non-existent or masked.
9 VCC1 P Primary Side Power Supply. Connect a 3V to 5.5V power supply to VCC1. Bypass VCC1 to GND1 with ceramic bulk capacitance as close to the VCC1 pin as possible.
10 ASC I Active Short Circuit Control Input. ASC sets the drive state when ASC_EN is high. If ASC is high, OUTH is pulled high. If ASC is low, OUTL is pulled low.
11 IN– I Negative PWM Input. IN- is connected to the IN+ from the opposite arm of the half-bridge. If IN+ and IN- overlap, the Shoot Through Protection (STP) fault is asserted.
12 IN+ I Positive PWM Input. IN+ drives the state of the driver output. With the driver enabled, when IN+ is high, OUTH is pulled high. When IN+ is low, OUTL is pulled low. Drive IN+ with a 1kHz to 50kHz PWM signal, with a logic level determined by the VCC1 voltage. IN+ is connected to the IN- of the opposite arm of the half-bridge. If IN+ and IN- overlap, the Shoot Through Protection (STP) fault is asserted.
13 CLK I SPI Clock. CLK is the clock signal for the main SPI interface. The SPI interface operates with clock rates up to 4MHz.
14 nCS I SPI Chip Selection Input. nCS is an active low input used to activate the SPI peripheral device. Drive nCS low during SPI communication. When nCS is high, the CLK and SDI inputs are ignored.
15 SDI I SPI Data Input. SDI is the data input for the main SPI interface. Data is sampled on the falling edge of CLK, SDI must be in a stable condition to ensure proper communication.
16 SDO O SPI Data Output. SDO is the data output for the main SPI interface. Data is clocked out on the falling edge of CLK, SDO is changed with a rising edge of CLK.
17 VREG1 P Internal Voltage Regulator Output. VREG1 provides a 1.8V rail for internal primary-side circuits. Bypass VREG1 to GND1 with at least 4.7µF of ceramic capacitance. Do not put any additional load on VREG1.
18 GND1 G Primary Side Ground. Connect all GND1 pins together and to the PCB ground plane on the primary side.
19 VEE2 P Secondary Negative Power Supply. Connect all VEE2 supply inputs together. Connect a -12V to 0V power supply to VEE2. The total voltage rail from VCC2 to VEE2 must not exceed 30V. Bypass VEE2 to GND2 with at least 1uF of ceramic capacitance as close to the VEE1 pin as possible.
20 VREG2 P Internal voltage regulator output. VREG2 provides a 1.8V rail for internal secondary-side circuits. Bypass VREG2 to VEE2 with at least 4.7µF of ceramic capacitance. Do not put any additional load on VREG2.
21 AI6 I Analog Input 6. AI6 is a multi-function input. It is configurable as an input to the internal ADC, a power FET current sense protection comparator input, and an ASC input for the secondary side.
22 AI5 I Analog Input 5. AI5 is a multi-function input. It is configurable as an input to the internal ADC, a power FET over temperature protection comparator input, and an ASC_EN input for the secondary side.
23 AI4 I Analog Input 4. AI4 is a multi-function input. It is configurable as an input to the internal ADC and a power FET current sense protection comparator input.
24 AI3 I Analog Input 3. AI3 is a multi-function input. It is configurable as an input to the internal ADC and a power FET current sense protection comparator input.
25 AI2 I Analog Input 2. AI2 is a multi-function input. It is configurable as an input to the internal ADC and a power FET current sense protection comparator input.
26 AI1 I Analog Input 1. AI1 is a multi-function input. It is configurable as an input to the internal ADC and a power FET current sense protection comparator input.
27 VREF P Internal ADC Voltage Regulator Output. VREF provides an internal 4V, reference for the ADC. Bypass VREF to GND2 with at least 1uF of ceramic capacitance. If an external reference is desired, disable the internal VREF using the SPI register, and connect a 4V reference supply to VREF. Loads up to 5mA on VREF are allowed.
28 GND2 G Gate Drive Common Input. Connect GND2 to the power FET source/ IGBT emitter. All AIx inputs, VREF, and DESAT are referenced to GND2.
29 CLAMP IO Miller Clamp Input. The CLAMP input is used to hold the gate of the power FET strongly to VEE2 while the power FET is "off". CLAMP is configurable as an internal Miller clamp, or to drive an external clamping circuit. When using the internal clamping function, connect CLAMP directly the power FET gate. When configured as an external clamp, connect CLAMP to the gate of an external pulldown MOSFET.
30 VEE2 P Secondary negative power supply. Connect all VEE2 supply inputs together. Connect a -12V to 0V power supply to VEE2. The total voltage rail from VCC2 to VEE2 must not exceed 30V. Bypass VEE2 to GND2 with at least 1uF of ceramic capacitance as close to the VEE2 pin as possible. Additional capacitance may be needed depending on the required drive current.
31 OUTL O Negative Gate Drive Voltage Output. When the driver is active, OUTL drives the gate of the power FET low when INP is low. Connect OUTL to the gate of the power FET through a gate resistor. The value of the gate resistor is chosen based on the slew rate required for the application.
32 OUTH O Positive Gate Drive Voltage Output. When the driver is active, OUTH drives the gate of the power FET high when INP is high. Connect OUTH to the gate of the power FET through a gate resistor. The value of the gate resistor is chosen based on the slew rate required for the application.
33 VBST P Bootstrap Supply. VBST supplies power for the OUTH drive. Connect a 0.1µF ceramic capacitor between VBST and OUTH.
34 VCECLP I VCE Clamp Input. VCECLP clamps to a diode above the VCC2 rail and indicates a fault when the voltage at VCECLP is above the VCECLPth threshold. Bypass VCECLP to VEE2 with ceramic capacitor and, in parallel, connect a resistor. Additionally, connect VCECLP to the anode of a zener diode to the collector of the power FET.
35 VCC2 P Secondary Positive Power Supply. Connect a 15V to 30V power supply to VCC2. The total voltage rail from VCC2 to VEE2 must not exceed 30V. Bypass VCC2 to GND2 and VCC2 to VEE2 with bulk ceramic capacitance as close to the VCC2 pin as possible. Additional capacitance may be needed depending on the required drive current.
36 DESAT I Desaturation based Short Circuit Detection Input. DESAT is used to detect a short circuit in the power FET. Bypass DESAT to GND2 with a ceramic capacitor to program the DESAT blanking time. In parallel, connect a schottky diode with the cathode connected to the DESAT. Additionally, connect DESAT to a resistor to the anode of a diode to the collector of the power FET to adjust the DESAT protection threshold. DESAT detects a fault when the VCE voltage of the power FET exceeds the defined threshold while the power FET is on.
(1) P = Power, G = Ground, I = Input, O = Output, - = NA