JAJSPD9 December   2022 UCC5871-Q1

PRODUCTION DATA  

  1. 1特長
  2. 2アプリケーション
  3. 3概要
  4. 4Revision History
  5. 5Pin Configuration and Functions
  6. 6Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  SPI Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Component Placement
      2. 7.1.2 Grounding Considerations
      3. 7.1.3 High-Voltage Considerations
      4. 7.1.4 Thermal Considerations
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS SPECIFICATION UNIT
PACKAGE SPECIFICATIONS
CLR External clearance(1) Shortest terminal-to-terminal distance through air 8 mm
CPG External creepage(1) Shortest terminal-to-terminal distance across the package surface 8 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) > 17 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 600 V
Material group According to IEC60664-1 I
Overvoltage category Rated mains voltage ≤ 600  VRMS I-IV
Rated mains voltage ≤ 1000  VRMS I-III
Test 1
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 2121 VPK
VIOWM Maximum isolation working voltage AC voltage (sine wave); time-dependent dielectric breakdown (TDDB) test 1500 VRMS
DC voltage 2121 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM,
t=60s (qualification);
VTEST = 1.2 x VIOTM,
t=1s (100% production)		 8000 VPK
VIOSM Maximum surge isolation voltage Test method per IEC 62368-1, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM 8000 VPK
qpd Apparent charge Method a: After I/O safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
≤5

 pC
Method a: After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
≤5
Method b1: At routine test (100% production) and preconditioning (type test),
Vini = 1.2 x VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1s		 ≤5
Test 2
CIO Barrier capacitance, input to output(2) VIO = 0.4 × sin (2 πft), f = 1 MHz 2 pF
RIO Insulation resistance, input to output(2) VIO = 500 V,  TA = 25°C 10^12 Ω
VIO = 500 V,  100°C ≤ TA ≤ 125°C 10^11
VIO = 500 V at  TS = 150°C 10^9
VISO Withstand isolation voltage VTEST = VISO = VRMS, t = 60 s (qualification),
VTEST = 1.2 × VISO = VRMS, t = 1 s (100% production)		 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator onthe printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.Techniques such as inserting grooves, ribs, or both on a printed-circuit board are used to help increase these specifications.
(2) All pins on each side of the barrier tied together creating a two-pin device.