It is essential to confine the high peak currents that charge and discharge the transistor gates to a minimal physical area. This decreases the loop inductance and minimize noise on the gate terminals of the transistors. The gate driver must be placed as close as possible to the transistors.
Ensure a small loop area/inductance between VCP and VCC2.
Analog signals measured with the integrated ADC on AI1 and AI2 pins must be
effectively isolated from high gate switching currents in GND2 net. It is
recommended to create Kelvin connections for these measurements to reduce impact
of ground bounce caused by high di/dt in the gate drive loop.