JAJSK73J
March 2012 – November 2021
UCD3138
PRODUCTION DATA
1
特長
2
アプリケーション
3
概要
4
機能ブロック図
5
Revision History
6
Device Comparison Table
6.1
Product Family Comparison
6.2
Product Selection Matrix
7
Pin Configuration and Functions
7.1
UCD3138RGC 64 QFN Pin Attributes
7.2
UCD3138RHA, UCD3138RMH and UCD3138RJA Pin Attributes
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing and Switching Characteristics
8.7
Power Supply Sequencing
8.8
Peripherals
8.8.1
Digital Power Peripherals (DPPs)
8.8.1.1
Front End
8.8.1.2
DPWM Module
8.8.1.3
DPWM Events
8.8.1.4
High Resolution DPWM
8.8.1.5
Oversampling
8.8.1.6
DPWM Interrupt Generation
8.8.1.7
DPWM Interrupt Scaling/Range
8.9
Typical Temperature Characteristics
9
Detailed Description
9.1
Overview
9.2
ARM Processor
9.3
Memory
9.3.1
CPU Memory Map and Interrupts
9.3.2
Boot ROM
9.3.3
Customer Boot Program
9.3.4
Flash Management
9.4
System Module
9.4.1
Address Decoder (DEC)
9.4.2
Memory Management Controller (MMC)
9.4.3
System Management (SYS)
9.4.4
Central Interrupt Module (CIM)
9.5
Feature Description
9.5.1
Sync FET Ramp and IDE Calculation
9.5.2
Automatic Mode Switching
9.5.2.1
Phase Shifted Full Bridge Example
9.5.2.2
LLC Example
9.5.2.3
Mechanism for Automatic Mode Switching
9.5.3
DPWMC, Edge Generation, IntraMux
9.5.4
Filter
9.5.4.1
Loop Multiplexer
9.5.4.2
Fault Multiplexer
9.5.5
Communication Ports
9.5.5.1
SCI (UART) Serial Communication Interface
9.5.5.2
PMBUS
9.5.5.3
General Purpose ADC12
9.5.5.4
Timers
9.5.5.4.1
24-bit PWM Timer
9.5.5.4.2
16-Bit PWM Timers
9.5.5.4.3
Watchdog Timer
9.5.6
Miscellaneous Analog
9.5.7
Package ID Information
9.5.8
Brownout
9.5.9
Global I/O
9.5.10
Temperature Sensor Control
9.5.11
I/O Mux Control
9.5.12
Current Sharing Control
9.5.13
Temperature Reference
9.6
Device Functional Modes
9.6.1
Normal Mode
9.6.2
Phase Shifting
9.6.3
DPWM Multiple Output Mode
9.6.4
DPWM Resonant Mode
9.6.5
Triangular Mode
9.6.6
Leading Edge Mode
10
Application and Implementation
10.1
Application Information
10.2
Typical Application
10.2.1
Design Requirements
10.2.2
Detailed Design Procedure
10.2.2.1
PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
10.2.2.2
DPWM Initialization for PSFB
10.2.2.3
DPWM Synchronization
10.2.2.4
Fixed Signals to Bridge
10.2.2.5
Dynamic Signals to Bridge
10.2.2.6
System Initialization for PCM
10.2.2.6.1
Use of Front Ends and Filters in PSFB
10.2.2.6.2
Peak Current Detection
10.2.2.6.3
Peak Current Mode (PCM)
10.2.3
Application Curves
11
Power Supply Recommendations
11.1
Introduction To Power Supply and Layout Recommendations
11.2
3.3-V Supply Pins
11.3
Recommendation for V33 Ramp up Slew Rate for UCD3138 and UCD3138064
11.4
Recommendation for RC Time Constant of RESET Pin for UCD3138 and UCD3138064
12
Layout
12.1
Layout Guidelines
12.1.1
EMI and EMC Mitigation Guidelines
12.1.2
BP18 Pin
12.1.3
Additional Bias Guidelines
12.1.4
UCD3138 Pin Connection Recommendation
12.1.4.1
Current Amplifier With EADC Connection
12.1.4.2
DPWM Synchronization
12.1.4.3
GPIOS
12.1.4.4
DPWM PINS
12.1.4.5
EAP and EAN Pins
12.1.4.6
ADC Pins
12.1.5
UART Communication Port
12.1.6
Special Considerations
12.2
Layout Example
12.2.1
UCD3138 and UCD3138064 40 Pin
12.2.2
UCD3138 and UCD3138064 64 Pin
13
Device and Documentation Support
13.1
Device Support
13.1.1
Code Composer Studio
13.1.2
Tools and Documentation
13.2
Documentation Support
13.2.1
References
13.3
Receiving Notification of Documentation Updates
13.4
サポート・リソース
13.5
Trademarks
13.6
Electrostatic Discharge Caution
13.7
Glossary
14
Mechanical Packaging and Orderable Information
14.1
Packaging Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RJA|40
MPQF467A
RMH|40
MPQF388A
RGC|64
MPQF125F
RHA|40
MPQF135D
サーマルパッド・メカニカル・データ
RJA|40
QFND826
RGC|64
QFND102O
発注情報
jajsk73j_oa
jajsk73j_pm
12.2.1
UCD3138 and UCD3138064 40 Pin
Figure 12-9
Power and Ground Schematic for UCD3138 and UCD3138064 40 Pin
Table 12-1 Power and Ground Connection Components for UCD3138 and UCD3138064 40 Pin
COMPONENT
VALUE
C1
1 µF
C3
2.2 µF
R1
2.2 kΩ
C4
4.7 µF
C5
10 nF
C7
10 nF
C8
1 µF
C9
10 nF
C10
4.7 µF
R2
1 Ω
C11
10 µF
C12
10 µF
C13
2.2 µF
Figure 12-10
UCD3138 and UCD3138064 40 Pin Layout Top Layer
Figure 12-11
UCD3138 and UCD3138064 40 Pin Layout Internal SGND Layer