JAJSLS2D march   2013  – april 2021 UCD3138064

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Functional Block Diagram
  6. 5 Revision History
  7. 6 Device Options
    1. 6.1 Device Comparison Table
    2. 6.2 Product Selection Matrix
  8. 7 Pin Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Functions
  9. 8 Specifications
    1. 8.1  Absolute Maximum Ratings #GUID-DB56AA00-A5E9-4426-9853-ACC9CCD10656/SLUSB727999
    2. 8.2  Handling Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Timing Characteristics
    7. 8.7  PMBus/SMBus/I2C Timing
    8. 8.8  Power On Reset (POR) / Brown Out Reset (BOR)
    9. 8.9  Typical Clock Gating Power Savings
    10. 8.10 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 ARM Processor
      2. 9.1.2 Memory
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  System Module
        1. 9.3.1.1 Address Decoder (DEC)
        2. 9.3.1.2 Memory Management Controller (MMC)
        3. 9.3.1.3 System Management (SYS)
        4. 9.3.1.4 Central Interrupt Module (CIM)
      2. 9.3.2  Peripherals
        1. 9.3.2.1 Digital Power Peripherals
          1. 9.3.2.1.1 Front End
          2. 9.3.2.1.2 DPWM Module
          3. 9.3.2.1.3 DPWM Events
          4. 9.3.2.1.4 High Resolution DPWM
          5. 9.3.2.1.5 Over Sampling
          6. 9.3.2.1.6 DPWM Interrupt Generation
          7. 9.3.2.1.7 DPWM Interrupt Scaling/Range
      3. 9.3.3  Automatic Mode Switching
        1. 9.3.3.1 Phase Shifted Full Bridge Example
        2. 9.3.3.2 LLC Example
        3. 9.3.3.3 Mechanism For Automatic Mode Switching
      4. 9.3.4  DPWMC, Edge Generation, Intramux
      5. 9.3.5  Filter
        1. 9.3.5.1 Loop Multiplexer
        2. 9.3.5.2 Fault Multiplexer
      6. 9.3.6  Communication Ports
        1. 9.3.6.1 SCI (UART) Serial Communication Interface
        2. 9.3.6.2 PMBUS/I2C
        3. 9.3.6.3 SPI
      7. 9.3.7  Real Time Clock
      8. 9.3.8  Timers
        1. 9.3.8.1 24-Bit Timer
        2. 9.3.8.2 16-Bit PWM Timers
        3. 9.3.8.3 Watchdog Timer
      9. 9.3.9  General Purpose ADC12
      10. 9.3.10 Miscellaneous Analog
      11. 9.3.11 Brownout
      12. 9.3.12 Global I/O
      13. 9.3.13 Temperature Sensor Control
      14. 9.3.14 I/O Mux Control
      15. 9.3.15 Current Sharing Control
      16. 9.3.16 Temperature Reference
    4. 9.4 Device Functional Modes
      1. 9.4.1 DPWM Modes Of Operation
        1. 9.4.1.1 Normal Mode
        2. 9.4.1.2 Phase Shifting
        3. 9.4.1.3 DPWM Multiple Output Mode
        4. 9.4.1.4 DPWM Resonant Mode
      2. 9.4.2 Triangular Mode
      3. 9.4.3 Leading Edge Mode
    5. 9.5 Memory
      1. 9.5.1 Register Maps
        1. 9.5.1.1 CPU Memory Map and Interrupts
          1. 9.5.1.1.1 Memory Map (After Reset Operation)
          2. 9.5.1.1.2 Memory Map (Normal Operation)
          3. 9.5.1.1.3 Memory Map (System and Peripherals Blocks)
        2. 9.5.1.2 Boot ROM
        3. 9.5.1.3 Customer Boot Program
        4. 9.5.1.4 Flash Management
        5. 9.5.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
  11. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 10.2.2.2 DPWM Initialization for PSFB
          1. 10.2.2.2.1 DPWM Synchronization
        3. 10.2.2.3 Fixed Signals to Bridge
        4. 10.2.2.4 Dynamic Signals to Bridge
        5. 10.2.2.5 System Initialization for PCM
          1. 10.2.2.5.1 Use of Front Ends and Filters in PSFB
          2. 10.2.2.5.2 Peak Current Detection
          3. 10.2.2.5.3 Peak Current Mode (PCM)
      3. 10.2.3 Application Curves
  12. 11Power Supply Recommendations
    1. 11.1 Introduction To Power Supply and Layout Recommendations
    2. 11.2 3.3-V Supply Pins
    3. 11.3 Recommendation for V33 Ramp up Slew Rate for UCD3138 and UCD3138064
    4. 11.4 Recommendation for RC Time Constant of RESET Pin for UCD3138 and UCD3138064
  13. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 EMI and EMC Mitigation Guidelines
      2. 12.1.2 BP18 Pin
      3. 12.1.3 Additional Bias Guidelines
      4.      UCD3138 Pin Connection Recommendation
        1. 12.1.4.1 Current Amplifier With EADC Connection
        2. 12.1.4.2 DPWM Synchronization
        3. 12.1.4.3 External Clock
        4. 12.1.4.4 GPIOS
        5. 12.1.4.5 DPWM PINS
        6. 12.1.4.6 EAP and EAN Pins
        7. 12.1.4.7 ADC Pins
          1. 12.1.4.7.1 RESET Pin
      5. 12.1.4 UART Communication Port
      6.      Special Considerations
    2. 12.2 Layout Example
      1. 12.2.1 UCD3138 and UCD3138064 40 Pin
      2. 12.2.2 UCD3138 and UCD3138064 64 Pin
  14. 13Device and Documentation Support
    1. 13.1 Device Support
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Trademarks
    4. 13.4 静電気放電に関する注意事項
    5. 13.5 用語集
  15. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.2 Pin Functions

UCD3138064RGC QFN 64 Pin Attributes
PINPRIMARY ASSIGNMENTALTERNATE ASSIGNMENTCONFIGURABLE
AS A GPIO?
NUMBERNAMENO. 1NO. 2NO. 3NO. 4
1AGNDAnalog ground
2AD1312-bit ADC, Ch 13, comparator E, I-shareDAC output
3AD1212-bit ADC, Ch 12
4AD1012-bit ADC, Ch 10
5AD0712-bit ADC, Ch 7, Connected to comparator F and reference to comparator GDAC output
6AD0612-bit ADC, Ch 6, Connected to comparator FDAC output
7AD0412-bit ADC, Ch 4, Connected to comparator DDAC output
8AD0312-bit ADC, Ch 3, Connected to comparator B and C
9V33DIODigital I/O 3.3V core supply
10DGNDDigital ground
11RESETDevice Reset Input, active low
12ADC_EXTADC conversion external trigger inputTCAPSYNCPWM0Yes
13SCI_RX0SCI RX 0Yes
14SCI_TX0SCI TX 0Yes
15PMBUS_CLKPMBUS Clock (Open Drain)SCI TX 0Yes
16PMBUS_DATAPMBus data (Open Drain)SCI RX 0Yes
17DPWM0ADPWM 0A outputYes
18DPWM0BDPWM 0B outputYes
19DPWM1ADPWM 1A outputYes
20DPWM1BDPWM 1B outputYes
21DPWM2ADPWM 2A outputYes
22DPWM2BDPWM 2B outputYes
23DPWM3ADPWM 3A outputYes
24DPWM3BDPWM 3B outputYes
25DGNDDigital ground
26SYNCDPWM Synchronize pinTCAPADC_EXT_TRIGPWM0Yes
27PMBUS_ALERTPMBus Alert (Open Drain)Yes
28PMBUS_CTRLPMBus Control (Open Drain)Yes
29SCI_TX1SCI TX 1PMBUS_ALERTYes
30SCI_RX1SCI RX 1PMBUS_CTRLYes
31PWM0General purpose PWM 0Yes
32PWM1General purpose PWM 1Yes
33DGNDDigital ground
34INT_EXTExternal InterruptYes
35FAULT0External fault input 0SPI_CSI2C_DATAYes
36FAULT1External fault input 1SPI_CLKI2C_CLKYes
37TCK(1)JTAG TCK (for manufacturer test only)TCAPSYNCPWM0Yes
38TDO(1)JTAG TDO (for manufacturer test only)SCI_TX0PMBUS_ALERTFAULT0SPI_MOSIYes
39TDI(1)JTAG TDI (for manufacturer test only)SCI_RX0PMBUS_CTRLFAULT1SPI_MISOYes
40TMS(1)JTAG TMS (for manufacturer test only)Yes
41TCAPTimer capture inputYes
42FAULT2External fault input 2Yes
43FAULT3External fault input 3Yes
44DGNDDigital ground
45V33DIODigital I/O 3.3 V core supply
46BP181.8V Bypass
47V33DDigital 3.3V core supply
48AGNDSubstrate analog ground
49AGNDAnalog ground
50EAP0Channel #0, differential analog voltage, positive input
51EAN0Channel #0, differential analog voltage, negative input
52EAP1Channel #1, differential analog voltage, positive input
53EAN1Channel #1, differential analog voltage, negative input
54EAP2Channel #2, differential analog voltage, positive input
55EAN2Channel #2, differential analog voltage, negative input
56AGNDAnalog ground
57V33AAnalog 3.3 V supply
58AD0012-bit ADC, Ch 0, Connected to current source
59AD0112-bit ADC, Ch 1, Connected to current source
60AD0212-bit ADC, Ch 2, Connected to comparator A, I-share
61AD0512-bit ADC, Ch 5
62AD0812-bit ADC, Ch 8
63AD0912-bit ADC, Ch 9
64AD1112-bit ADC, Ch 11
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.
UCD3138064RMH and UCD3138064RJA QFN 40 Pin Attributes
PINPRIMARY ASSIGNMENTALTERNATE ASSIGNMENTCONFIGURABLE
AS A GPIO?
NUMBERNAMENO. 1NO. 2NO. 3
1AGNDAnalog ground
2AD1312-bit ADC, Ch 13, Connected to comparator E, I-share

DAC Output

3AD0612-bit ADC, Ch 6, Connected to comparator F

DAC Output

4AD0412-bit ADC, Ch 4, Connected to comparator D

DAC Output

5AD0312-bit ADC, Ch 3, Connected to comparator B & C
6DGNDDigital ground
7RESETDevice Reset Input, active low
8ADC_EXT_TRIGADC conversion external trigger inputTCAPSYNCPWM0Yes
9PMBUS_CLKPMBUS Clock (Open Drain)SCI_TX0Yes
10PMBUS_DATAPMBUS Data (Open Drain)SCI_RX0Yes
11DPWM0ADPWM 0A outputYes
12DPWM0BDPWM 0B outputYes
13DPWM1ADPWM 1A outputYes
14DPWM1BDPWM 1B outputYes
15DPWM2ADPWM 2A outputYes
16DPWM2BDPWM 2B outputYes
17DPWM3ADPWM 3A outputYes
18DPWM3BDPWM 3B outputYes
19PMBUS_ALERTPMBus Alert (Open Drain)Yes
20PMBUS_CTRLPMBus Control (Open Drain)Yes
21TCK(1)JTAG TCK (for manufacturer test only)TCAPSYNCPWM0Yes
22TDO(1)JTAG TDO (for manufacturer test only)SCI TX0PMBUS_ALERTFAULT0Yes
23TDI(1)JTAG TDI (for manufacturer test only)SCI_RX0PMBUS_CTRLFAULT1Yes
24TMS(1)JTAG TMS (for manufacturer test only)Yes
25FAULT2External fault input 2Yes
26DGNDDigital ground
27V33DDigital 3.3 V core supply
28BP181.8V Bypass
29AGNDSubstrate analog ground
30AGNDAnalog ground
31EAP0Channel #0, differential analog voltage, positive input
32EAN0Channel #0, differential analog voltage, negative input
33EAP1Channel #1, differential analog voltage, positive input
34EAN1Channel #1, differential analog voltage, negative input
35EAP2Channel #2, differential analog voltage, positive input
(Recommended for peak current mode control)
36AGNDAnalog ground
37V33AAnalog 3.3 V supply
38AD0012-bit ADC, Ch 0, Connected to current source
39AD0112-bit ADC, Ch 1, Connected to current source
40AD0212-bit ADC, Ch 2, Connected to comparator A, I-share
Corner
NA		Corner anchor pin
(RMH only)		All four anchors should be soldered and tied to GND
(1) Fusion Digital Power based debug tools are recommended instead of JTAG.