SLUSCA5B December   2015  – January 2017 UCD3138064A

PRODUCTION DATA.  

  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2Revision History
  3. 3Device Options
    1. 3.1 Device Comparison Table
  4. 4Pin Configuration and Functions
    1. 4.1 Pin Diagrams
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Characteristics
    7. 5.7 PMBus/SMBus/I2C Timing
    8. 5.8 Parametric Measurement Information
    9. 5.9 Typical Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 ARM Processor
    3. 6.3 Memory
    4. 6.4 Feature Description
      1. 6.4.1  System Module
        1. 6.4.1.1 Address Decoder (DEC)
        2. 6.4.1.2 Memory Management Controller (MMC)
        3. 6.4.1.3 System Management (SYS)
        4. 6.4.1.4 Central Interrupt Module (CIM)
      2. 6.4.2  Peripherals
        1. 6.4.2.1 Digital Power Peripherals
          1. 6.4.2.1.1 Front End
          2. 6.4.2.1.2 DPWM Module
          3. 6.4.2.1.3 DPWM Events
          4. 6.4.2.1.4 High Resolution DPWM
          5. 6.4.2.1.5 Over Sampling
          6. 6.4.2.1.6 DPWM Interrupt Generation
          7. 6.4.2.1.7 DPWM Interrupt Scaling/Range
      3. 6.4.3  Synchronous Rectifier Dead Time Optimization Peripheral
      4. 6.4.4  Automatic Mode Switching
        1. 6.4.4.1 Phase Shifted Full Bridge Example
        2. 6.4.4.2 LLC Example
        3. 6.4.4.3 Mechanism For Automatic Mode Switching
      5. 6.4.5  DPWMC, Edge Generation, IntraMux
      6. 6.4.6  Filter
        1. 6.4.6.1 Loop Multiplexer
        2. 6.4.6.2 Fault Multiplexer
      7. 6.4.7  Communication Ports
        1. 6.4.7.1 SCI (UART) Serial Communication Interface
        2. 6.4.7.2 PMBUS/I2C
        3. 6.4.7.3 SPI
      8. 6.4.8  Timers
        1. 6.4.8.1 24-Bit Timer
        2. 6.4.8.2 16-Bit PWM Timers
        3. 6.4.8.3 Watchdog Timer
      9. 6.4.9  General Purpose ADC12
      10. 6.4.10 Miscellaneous Analog
      11. 6.4.11 Brownout
      12. 6.4.12 Global I/O
      13. 6.4.13 Temperature Sensor Control
      14. 6.4.14 I/O Mux Control
      15. 6.4.15 Current Sharing Control
      16. 6.4.16 Temperature Reference
    5. 6.5 Device Functional Modes
      1. 6.5.1 DPWM Modes Of Operation
        1. 6.5.1.1 Normal Mode
        2. 6.5.1.2 Phase Shifting
        3. 6.5.1.3 DPWM Multiple Output Mode
        4. 6.5.1.4 DPWM Resonant Mode
      2. 6.5.2 Triangular Mode
      3. 6.5.3 Leading Edge Mode
    6. 6.6 Memory
      1. 6.6.1 Register Maps
        1. 6.6.1.1 CPU Memory Map and Interrupts
          1. 6.6.1.1.1 Memory Map (After Reset Operation)
          2. 6.6.1.1.2 Memory Map (Normal Operation)
          3. 6.6.1.1.3 Memory Map (System and Peripherals Blocks)
        2. 6.6.1.2 Boot ROM
        3. 6.6.1.3 Customer Boot Program
        4. 6.6.1.4 Flash Management
        5. 6.6.1.5 Synchronous Rectifier MOSFET Ramp and IDE Calculation
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 PCMC (Peak Current Mode Control) PSFB (Phase Shifted Full Bridge) Hardware Configuration Overview
        2. 7.2.2.2 DPWM Initialization for PSFB
          1. 7.2.2.2.1 DPWM Synchronization
        3. 7.2.2.3 Fixed Signals to Bridge
        4. 7.2.2.4 Dynamic Signals to Bridge
        5. 7.2.2.5 System Initialization for PCM
          1. 7.2.2.5.1 Use of Front Ends and Filters in PSFB
          2. 7.2.2.5.2 Peak Current Detection
          3. 7.2.2.5.3 Peak Current Mode (PCM)
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 Device Grounding and Layout Guidelines
        2. 7.2.5.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Device Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Community Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  9. 9Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

2 Revision History

Changes from A Revision (June 2016) to Revision

    Changes from * Revision (December 2015) to A Revision

    • Deleted WQFN (40) from the Device Information tableGo
    • Deleted the 3138064, 3138064A RMH (40 Pin) column from the Device Comparison TableGo
    • Deleted the Product Selection Matrix table Go
    • Deleted the 40-Pin QFN RMH Package from the Pin Diagrams sectionGo
    • Deleted VQFN (RGZ) and WQFN (RMH) packages from the Thermal Information tableGo
    • Added updated V33 slew rate values in the Device Grounding and Layout Guidelines section.Go
    • Changed the capacitor value from 0.22 µF to 2.2 µF.Go
    • Added BP18 decoupling requirements updated Go
    • Added GPIO settings for unused pins Go
    • Changed New PCB Layout image Go