JAJSMV1E March   2005  – November 2021 UCD7100

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input
      2. 9.3.2 Current Sensing and Protection
      3. 9.3.3 Handshaking
      4. 9.3.4 Driver Output
      5. 9.3.5 Source/Sink Capabilities During Miller Plateau
      6. 9.3.6 Drive Current and Power Requirements
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation with VDD < 4.25 V (minimum VDD)
      2. 9.4.2 Operation with IN Pin Open
      3. 9.4.3 Operation with ILIM Pin Open
      4. 9.4.4 Operation with ILIM Pin High
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Supply
    2. 11.2 Reference and External Bias Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Considerations
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
    2. 13.2 Third-Party Products Disclaimer
    3. 13.3 Documentation Support
      1. 13.3.1 Related Documentation
    4. 13.4 Receiving Notification of Documentation Updates
    5. 13.5 サポート・リソース
    6. 13.6 Trademarks
    7. 13.7 Glossary
    8. 13.8 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • PWP|14
サーマルパッド・メカニカル・データ
発注情報

7 Pin Configuration and Functions

GUID-CEE0D36E-DCB6-45D3-AEA4-0AE17518663E-low.gifFigure 7-1 PWP14 PINSTop View
Table 7-1 Pin Functions
UCD7100 PIN NAME TYPE FUNCTION
HTSSOP-14 PIN NO. DFN-14 PIN NO.
1 1 VDD I Supply input pin to power the driver. The UCD7K devices accept an input range of 4.25 V to 15 V. Bypass the pin with at least 4.7 µF of capacitance.
2 2 IN I The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry from any external noise.
3 3 3V3 O Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. Place 0.22-µF of ceramic capacitance from the pin to ground.
4 4 AGND — Analog ground return.
5 5 CLF O Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is latched high until the UCD7K device receives the next rising edge on the IN pin.
6 6 ILIM I Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V and 1.0 V.
7 7 NC — No Connection.
8 8 CS I Current sense pin. Fast current limit comparator connected to the CS pin is used to protect the power stage by implementing cycle-by-cycle current limiting.
9 9 PGND — Power ground return. Connect the two PGNDs together. These ground pins should be connected very closely to the source of the power MOSFET.
10 10 PGND — Power ground return. Connect the two PGNDs together. These ground pins should be connected very closely to the source of the power MOSFET.
11 11 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together.
12 12 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together.
13 13 PVDD I Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. Connect the two PVDD pins together.
14 14 PVDD I Supply pin provides power for the output drivers. It is not connected internally to the VDD supply rail. Connect the two PVDD pins together.