The UCD7138 device is a 4-A and 6-A single-channel MOSFET driver with body-diode conduction sensing and reporting and is a high performance driver that allows the Texas Instruments UCD3138A digital PWM controller to achieve advanced synchronous-rectification (SR) control. The device contains a high-speed gate driver, a body-diode conduction-sensing circuit, and a turnon delay optimization circuit. The device is suitable for high-power, high-efficiency isolated converter applications where SR dead-time optimization is desired.
The UCD7138 device offers asymmetrical rail-to-rail 4-A source and 6-A sink peak-current drive capability. The short propagation delay and fast rise and fall time allows efficient operation at high frequencies. An internal high-speed comparator with a –150-mV threshold detects the body-diode conduction and reports the information to the UCD3138A digital-power controller. The UCD7138 device is capable of sensing body-diode conduction time as low as 10 ns. The SR turnon edge is optimized by the UCD7138 device. The SR turnoff edge is optimized by the UCD3138A digital-power controller which analyzes the body-diode conduction information reported by the UCD7138 DTC pin.
The benefits of the chipset include maximizing system efficiency by minimizing body-diode conduction time, robust and fast negative-current protection, and a simple interface.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
UCD7138 | WSON (6) | 3.00 mm × 3.00 mm |
Changes from A Revision (April 2015) to B Revision
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | IN | I | Input: Gate driver input. This pin should be connected directly to the DPWM output of the digital controller. |
2 | DTC | O | Body-diode conduction-time report: Standard digital IO. Pulled high internally. Output low when the body diode is conducting. This pin should be connected to the DTC0 or DTC1 pin on UCD3138A. |
3 | VCC | P | IC supply: External bias supply input. The supply range is 4.5-V to 18-V. A ceramic bypass capacitor of at least 1 µF should be placed as close as possible to the VCC pin and the thermal pad. Where possible, use thick & wide Cu connections. |
4 | OUT | O | Gate driver output: Integrated push-pull gate driver for one or more external power MOSFETs. Typical 4-A source and 6-A sink capability. This is a rail-to-rail output, with the rails defined by the voltages on VCC and GND. This pin should be connected to the gate terminal of the synchronous rectification MOSFET. |
5 | VD | I | Drain voltage: Connect this pin as close as possible to the controlled-MOSFET drain pad. This pin is internally connected to the diode conduction detection comparator. The comparator has a –0.15-V threshold to detect body-diode conduction. A 20-Ω resistor should be connected between the VD pin and MOSFET drain terminal to limit the current. The maximum voltage of the VD pin should not exceed 45 V. A simple external circuit can enable the usage of much higher voltages, see Figure 34. |
6 | CTRL | I | Rising edge optimization control: Connect this pin to ground to disable rising edge optimization. Leave this pin floating or connect it to logic high to enable rising edge optimization. |
— | Thermal Pad (GND) | — | Exposed thermal pad: The exposed pad on the bottom of the package enhances the thermal performance of the device. This pad is the device ground reference. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VCC | –0.3 | 20 | V |
IN, CRTL | –0.3 | 3.8 | ||
VD | –1 | 45 | ||
Maximum VCC continuous input current | DC current | 50 | mA | |
Output current, peak (pulse) | 6 | A | ||
Switching frequency, ƒS | 2000 | kHz | ||
Operating junction temperature, TJ | –40 | 125 | °C | |
Lead temperature, soldering, 10 s, T(SOL) | 300 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS–001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VCC | VCC input voltage from a low impedance source | 4.5 | 18 | V | |
VIN | Input voltage | 0 | 3.6 | V | |
C(BP) | VCC bypass capacitor | 1 | µF | ||
TJ | Operating junction temperature | –40 | 125 | °C |
THERMAL METRIC(1) | UCD7138 | UNIT | |
---|---|---|---|
DRS (WSON) | |||
6 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 73.4 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 84.2 | |
RθJB | Junction-to-board thermal resistance | 46.3 | |
ψJT | Junction-to-top characterization parameter | 2.6 | |
ψJB | Junction-to-board characterization parameter | 46.4 | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 12.4 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
VCC BIAS SUPPLY | ||||||
ICC(UV) | VCC current, undervoltage | VCC = 3.4 V | 122 | 186 | µA | |
ICC(ON) | VCC current, no switching | VCC = 12 V | 0.85 | 1.1 | mA | |
ICC(OPERATE) | VCC current, normal operation (1) | VCC = 12 V, C(LOAD) = 10 nF, ƒ = 100 kHz |
13 | 17 | mA | |
GATE INPUT (IN) | ||||||
VIH | Input signal high threshold | 1.93 | 2.03 | 2.10 | V | |
VIL | Input signal low threshold | 0.98 | 1.03 | 1.08 | V | |
VI(hys) | Input hysteresis | 0.90 | 1.00 | V | ||
DTC OUTPUT | ||||||
VOL(DTC) | Low level output voltage | 0.25 | V | |||
VOH(DTC) | High level output voltage | 2.5 | V | |||
IOH(DTC) | Output sinking current | 4 | mA | |||
IOL(DTC) | Output sourcing current | –4 | mA | |||
VDTC | Maximum DTC pin output voltage | 3.5 | 3.6 | V | ||
UNDERVOLTAGE LOCKOUT SECTION (UVLO) | ||||||
VCC(ON) | VCC turnon threshold | 3.30 | 3.80 | 4.30 | V | |
VCC(OFF) | VCC turnoff threshold | 3.10 | 3.56 | 4.02 | V | |
VCC(hys) | UVLO hysteresis | VCC(hys) = VCC(ON) – VCC(OFF) | 0.24 | V | ||
COMPARATOR | ||||||
VTH | Body diode conduction sensing threshold | –179 | –147 | –113 | mV | |
CI(VD–ground) | Differential input capacitance between VD and ground (1) | VD = –150 mV | 20 | pF | ||
GATE DRIVER | ||||||
VCC-VOH | Output high voltage | IOUT = –10 mA | 0.038 | 0.064 | V | |
VOL | Output low voltage | IOUT = 10 mA | 0.0025 | 0.009 | V | |
R(UP) | Pullup resistance | TA = 25°C, IOUT = –25 mA to –50 mA |
5 | 6.1 | Ω | |
TA = –40°C to 125°C, IOUT = –50 mA |
5 | 6.3 | Ω | |||
R(DOWN) | Pulldown resistance | TA = 25°C, IOUT = 25 mA to 50 mA |
0.31 | 0.44 | Ω | |
TA = –40°C to 125°C, IOUT = 50 mA |
0.33 | 0.45 | Ω | |||
IO(source) | Output peak current (source) (1) | C(LOAD) = 0.22 µF, ƒS = 1 kHz, 5-V output |
–4 | A | ||
IO(sink) | Output peak current (sink) (1) | C(LOAD) = 0.22 µF, ƒS = 1 kHz, 5-V output |
6 | A |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tr | Rise time | C(LOAD) =1 nF, VCC = 5 V, See Figure 1 and Figure 24 |
5 | 8 | ns | |
C(LOAD) =1 nF, VCC = 12 V, See Figure 1 and Figure 24 |
4 | 8 | ns | |||
tf | Fall time | C(LOAD)=1 nF, VCC = 5 V, See Figure 1 and Figure 24 |
3.36 | 5 | ns | |
C(LOAD)=1 nF, VCC = 12 V, See Figure 1 and Figure 24 |
3.5 | 5 | ns | |||
tw(VD) | Minimum VD pulse duration (width) that changes the DTC output state | VCC = 5 V | 10 | 23 | ns | |
VCC = 12 V | 10 | 23 | ns | |||
tw(IN) | Minimum IN duration (width) that changes OUT state | VCC = 5 V | 11 | 13 | ns | |
VCC = 12 V | 11 | 13 | ns | |||
td(1) | Gate driver turn on propagation delay | C(LOAD) = 1 nF, VIN = 0 V to 3.3 V, VCC = 5 V, VVD = –0.5 V, See Figure 1 and Figure 24 |
14 | 26.6 | ns | |
C(LOAD) = 1 nF, VIN = 0 V to 3.3 V, VCC = 12 V, VVD = –0.5 V, See Figure 1 and Figure 24 |
14 | 25 | ns | |||
td(2) | Gate driver turn off propagation delay | C(LOAD) = 1 nF, VIN = 3.3 V to 0 V, VCC = 5 V, See Figure 1 and Figure 24 |
14 | 22.9 | ns | |
C(LOAD) = 1 nF, VIN = 3.3 V to 0 V, VCC = 12 V, See Figure 1 and Figure 24 |
14 | 22 | ns | |||
td(COMP) | Body-diode conduction detection-comparator controlled-turnon propagation delay(1) | C(LOAD) = 1 nF, VIN = 3.3 V, VCC = 5 V, VVD = 2 V to –0.5 V, See Figure 24 | 28 | 36 | ns | |
C(LOAD) = 1 nF, VIN = 3.3 V, VCC = 12 V, VVD = 2 V to –0.5 V, See Figure 24 | 26 | 33 | ns | |||
td(DTC) | DTC output propagation delay | VCC = 5 V | 21 | 27 | ns | |
VCC = 12 V | 18 | 25 | ns |
VCC = 3.4 V |
VCC = 12 V | C(LOAD) = 10 nF | ƒ = 100 kHz |
No switching |
VCC = 12 V |
The UCD7138 low-side gate driver is a high-performance driver for secondary-side synchronous rectification with body-diode conduction sensing. The device is suitable for high-power high-efficiency isolated converter applications where dead-time optimization is desired. The body-diode conduction is sensed at the falling edge of the gate-drive signal and sent to the UCD3138A digital-power controller through one digital IO pin. The digital controller can adjust the dead-time setting based on this information. The body-diode conduction time is detected in a certain time window in the UCD3138A digital controller. This detection prevents reporting erroneous signals because of noise or reverse current. At the gate turnon edge, the UCD7138 gate driver optimizes the dead time by turning the gate on as soon as diode conduction is detected. The benefits of this driver to the system include, but are not limited to, improved efficiency, improved reliability, and ease of design.
The internal gate driver is a single-channel, high-speed gate driver suitable for both 12-V and 5-V drive. The gate driver offers 4-A source and 6-A sink (asymmetrical drive) peak drive current capability. The package and pin configuration provide minimum parasitic inductances to reduce rise and fall times and to limit ringing. Additionally, the short propagation delay with minimized tolerances and variations allows efficient operation at high frequencies. The 5-Ω and 0.35-Ω pull-up and pull-down resistances boost immunity to hard switching with high slew-rate dV and dt.
The internal body-diode conduction detector is a high-speed comparator with 20-ns propagation delay. The DTC output is internally pulled high by default. When body-diode conduction is sensed, DTC pin drives low.
In Figure 24, VDS is the drain-to-source voltage which is connected to the VD pin. The IN pin is the gate-driver input-command signal from the UCD3138A digital controller. The DTC pin is the sensed body-diode conduction. The OUT pin is the gate-driver output. The body-diode conduction detection comparator has a –150-mV threshold. When the body diode conducts, the DTC pin is low. If the body diode does not conduct, the DTC pin is high.
To improve noise immunity, the comparator output DTC is blanked when the gate driver output, OUT, is high. The DTC signal always outputs high when OUT is high.
Gate turnon is controlled by both the gate driver input, IN, and body-diode conduction. System robustness is enhanced through internal logic that guarantees that OUT is only allowed high if IN is also high. At the IN rising edge, the UCD7138 gate-driver analyzes the DTC signal and determines the required course of action. The OUT pin is sent high immediately if the DTC comparator output is low at the rising edge of the IN signal. If the DTC pin is high at the rising edge of the IN signal, OUT is held low until DTC goes low. To allow the gate turnon edge to optimize freely, setting the dead time between the primary side falling edge and the IN rising edge smaller than expected in the UCD3138A digital controller is recommended.
The gate turnoff edge is determined by the IN signal only. The gate is turned off immediately at the IN falling edge.
CTRL PIN CONFIGURATION | FUNCTION |
---|---|
0 V or ground | Turn-on optimization disabled |
3.3 V or floating | Turn-on optimization enabled |
The UCD7138 device has an internal undervoltage-lockout (UVLO) protection feature based on the VCC-pin voltage. Whenever the driver is in the UVLO condition (such as when the VCC voltage is less than VCC(ON) during power up or when the VCC voltage is less than VCC(OFF) during power down), the device holds all outputs low, regardless of the status of the inputs. The UVLO voltage is typically 3.8 V with a 240-mV hysteresis. This hysteresis helps prevent chatter when low VCC supply voltages have noise from the power supply and also when droops occur in the VCC bias voltage.
For example, at power up, the UCD7138 driver output remains low until the VCC voltage reaches the UVLO threshold. The magnitude of the OUT signal rises with VCC until steady-state VCC is reached. The output remains low until the UVLO threshold is reached. The DTC signal begins to rise when VCC begins to rise. The internal diode conduction detection comparator remains inactive until VCC passes VCC(ON) threshold.
The UCD7138 device features very-low quiescent supply current. The total supply current is the sum of the quiescent supply current, the average IOUT current from switching, and any current related to pull-up resistors on the unused input pin. Knowing the operating frequency (ƒS) and the MOSFET gate (QG) charge, the average IOUT current can be calculated as product of QG and ƒS.
The input pins of the UCD7138 device are based on a CMOS-compatible input-threshold logic that is independent of the VCC supply voltage. The logic-level thresholds can be conveniently driven with PWM control signals derived from 3.3-V.
The output stage of the UCD7138 device features a unique architecture on the pull-up structure. This architecture delivers the highest peak-source current when needed during the Miller-plateau region of the power switch turnon transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pull-up structure features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the N-Channel MOSFET is to provide a brief boost in the peak sourcing current to enable fast turnon. This boost occurs by briefly turning on the N-Channel MOSFET when the output is changing state from LOW to HIGH.
When the VCC voltage to the device has not reached the VCC(ON) threshold or has fallen below the UVLO threshold, VCC(OFF) , the device operates in the low-power UVLO mode. In this mode, most internal functions are disabled and the ICC current is very low. In UVLO mode, the OUT pin is held low. The device passes out of UVLO mode when the VCC voltage increases above the VCC(ON) threshold.
In this mode, the ICC current is higher because all internal control and timing functions are operating and the gate-driver output, OUT, is driving the controlled MOSFET for synchronous rectification. In this mode, the VCC current is the sum of ICC(ON) plus the average current required to drive the load on the OUT pin.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The UCD7138 device can be used in a wide range of applications. The device can be used on many center-tapped secondary-side rectification topologies. Specifically, the device can be used in half-bridge LLC converters. In these applications, the UCD3138A and UCD7138 chipset enables the synchronous rectifiers to closely approximate the behavior of an ideal diode which is difficult to do in an LLC converter because of the variations in the SR current-conduction time.
The UCD7138 and UCD3138A chipset together can provide an easy-to-use, high-performance and advanced SR-control solution. Without this solution, fine tuning is required for each operation region (including below resonant frequency, at resonant frequency, and above resonant frequency). For LLC converters in production, each power stage may have a different resonant frequency because of tolerances of circuit capacitors and inductors. Calibration is required for each converter to achieve high efficiency. With UCD7138 and UCD3138A advanced SR control, optimal SR operation is easily achieved for every converter without fine tuning and calibration of the resonant tank can be eliminated in production. For more information see Using UCD7138 and UCD3138A for Advanced Synchronous Rectification Control, SLUA737.
Figure 27 shows a typical half-bridge LLC application using the UCD7138 device as a secondary-side SR driver and the UCD3138A device as a controller.
In LLC converters, if the SRs are not well optimized, the SR conduction time can either be too long or too short. The duration of the body diode conduction time can be determined by examining the drain-to-source voltage of the MOSFET when it is off. The SR turnon edge is optimized by the UCD7138 device by turning the gate on as soon as body-diode conduction is sensed. The SR turnoff edge is determined when the UCD3138A digital controller analyzes the sensed body-diode conduction time. Figure 28 shows the typical drain-to-source waveforms on a half-bridge LLC converter and the desired waveforms.
As shown in Figure 29, when the SR pulse is on for too long, the drain-to-source voltage shoots up. The upper waveform in Figure 29 shows the SR current. The lower waveform shows the SR drain-to-source voltage. The black segment of the curves show when the SR MOSFET is on. The red and green segments of the curves show when the SR MOSFET is off. The SR current is positive at first, but continues to drop until it is negative. The drain-to-source voltage is close to 0 V when the SR MOSFET is on. As soon as the SR MOSFET is turned off, the negative current must reset. The capacitance across the drain and source terminal is charged, and the drain-to-source voltage increases. The green segments of the curves show when the negative current reset process is complete at which point the body diode of the MOSFET conducts briefly again.
For the UCD3138A device, a DTC detection window is generated at the falling edge of the gate drive command IN signal. Only during this detection window is the DTC low time counted by a 4-ns resolution timer capture inside the UCD3138A device. Figure 30 shows the simplified system block diagram. In the two body-diode conduction cases shown in Figure 31, the SR on time should be adjusted in different directions. The detection window identify that these two cases are different. If, during the detection window, a large amount of DTC low time is detected, and the SR turns off too early. If, during the detection window, no or very-short DTC low time is detected and the SR turns off too late.
The UCD3138A digital controller counts the body-diode conduction time of the current cycle and adjusts the SR on time of the next cycle. In Figure 32, the DTC0 and DTC1 signals are the body-diode conduction inputs received from the UCD7138 device. SR0_DPWM and SR1_DPWM are the DPWM waveforms for the SRs. The red and green dashed lines are moving edges controlled by both the UCD3138A digital-compensator output and the DTC interface. In each cycle, directly after the falling edge of the SR DPWM waveform, a detection window is generated for the body-diode conduction time. The detection window is defined by both DETECT_BLANK and DETECT_LEN registers. During this detection window, a 4-ns timer capture counts the conduction time of the body diode. The SR DPWM turnoff edge of the next cycle is then adjusted accordingly.
Figure 33 shows how the SR turnoff edge is adjusted based on the DTC measurement of the previous cycle. The A_CNT or B_CNT is the counted values of diode conduction time of two SRs which ranges from 0 to 127. The two types of SR control modes are automatic-control mode and manual-control mode. If manual-control mode is used, the SR on-time adjustment value is determined by the manual write register. If automatic-control mode is used, the UCD3138A digital controller automatically calculates the SR on-time adjustment amount for the next cycle. The body-diode conduction time at the falling edge of the SR gate is regulated to a target value by step-by-step edge adjustment in the UCD3138A device. The SR on time is reduced by a preprogrammed large amount, when the sensed body-diode conduction time is less than a programmable threshold. This reduction prevents the power supply from damaged caused by negative current in the SRs.
For more information on the DTC interface on UCD3138A see UCD7138 and UCD3138A for Advanced Synchronous Rectification Control, SLAU737 and UCD3138A Highly Integrated Digital Controller for Isolated Power, SLUSC66.
The input stage of the driver should be driven by a signal with fast rise and fall times. Caution must be exercised whenever the driver is used with slowly varying input signals, in situations where the device is located in a mechanical socket or PCB layout is not optimal (bad grounding, for example). Ground bounce is often caused by high di/dt current from the driver output, coupled with board-layout parasitic. The differential voltage between the input pin IN and ground pad GND may be modified by ground bounce and trigger an unintended change of output state. Because of short propagation delay, the unintended change of state can ultimately result in high-frequency oscillations, which increases power dissipation and can potentially damage the device. In the worst case, when a slow input signal is used and PCB layout is not optimal, adding a small capacitor (1 nF) between the input pin and ground very close to the driver device may be necessary.
The output of the gate driver (OUT) must be connected as close to the MOSFET gate as possible. A small resistor may be connected in between to reduce the high-frequency oscillations on the gate. Doing so can also slow down the gate transitions. The DTC detection windows inside UCD3138A may need some adjustment to compensate for the delay caused by the added resistor.
When the drain-to-source voltage is below 0 V, current flows out of the VD pin to the drain terminal of the MOSFET. This current flow must be limited to ensure proper operation of the device. The recommended current-limiting resistance value is 20Ω.
The highest voltage that can be applied to VD pin is 45 V which is good for applications where 40-V MOSFETs are used for the secondary-side SRs. If a higher voltage is required for VD pin, an external high-voltage blocking circuit can be used together with the UCD7138 device as shown in Figure 34. Depending on the required voltage rating, a different external high-voltage blocking MOSFET can be selected. Usually a small SOT-23 MOSFET can be used. In this circuit, the gate terminal of the external high-voltage blocking MOSFET is connected to VCC of the UCD7138 gate driver. The source terminal is connected with a current-limiting resistor to the VD pin of the UCD7138 device. The drain terminal is connected to the SR MOSFET drain terminal. When a low voltage is presented at the drain terminal, the blocking MOSFET is turned on because of the positive gate-to-source voltage. When the drain voltage becomes higher and higher, the source terminal voltage rises along with the drain terminal until the gate-to-source voltage falls below the threshold. When the source voltage is high enough so that the blocking MOSFET is turned off, the high voltage on the SR drain is blocked.
The DTC pin is the internal comparator output. This pin should be connected to the DTC0 or DTC1 pin on the UCD3138A device. To keep edges sharp, no filtering is recommended. If noise spikes are observed on the DTC signal, the blanking times in the UCD3138A device can be used to prevent the digital controller from sensing noise. This pin is not designed to drive large current. If filtering must be used, ensure that the sink and source current on this pin is within ±4 mA as specified in the
Electrical Characteristics table.
The turnon edge optimization is useful when a positive current flow is at the rising edge of SRs. To maximize the efficiency gain, the dead time between the falling edge of the primary and the rising edge of the secondary should be programmed to a smaller value than expected, so that the rising edge of the SRs can move freely by UCD7138.
The design procedure of an LLC converter with synchronous rectification can be greatly simplified by using the UCD7138 and UCD3138A chipset. The converter hardware and firmware can initially be designed without advanced SR optimization and then add SR optimization function in.
For more information on the UCD3138A-based digital LLC converter, UCD3138A Highly Integrated Digital Controller for Isolated Power, SLUSC66.
The body-diode conduction should be detected in a specific region for the system to operate correctly. The detection window is defined by a blanking time register DETECT_BLANK and a detection length register DETECT_LEN in the UCD3138A device. To set the detection window, let the LLC converter operate below resonant frequency. measure the VD, IN, and DTC waveforms on an oscilloscope. Use cursors to measure the time, t, difference between the IN falling edge and the starting point of body-diode conduction (first falling edge of DTC excluding noise spike). The blanking time should be set to be less than t. Usually the required blanking time is very short or non existent, so the blanking time can be set to around 10% of t. The detection window length can be set to a few times of the desired body-diode conduction time. For example, if the desired body-diode conduction time is 40 ns, the detection window length can be set to 120 ns. Make sure that the body-diode conduction is well covered inside the detection window when it is at an optimal value. The end point of the detection window should never exceed the first valley on the VD waveform to avoid errors in measurement (see Figure 35).
After the detection window is set, enable the DTC module in manual control mode. Set the offset in the manual control registers to 0. Change the input voltage and load current to different operation points to verify that the UCD3138A DTC module measures the correct values in the A_CNT and B_CNT registers. See the UCD3138A64 Programmer’s Manual, SLUUB54 for detailed register information.
The SR adjustment accumulator clamps defines the maximum SR turnoff edge offset from the calculated value from the UCD3138A compensator. The maximum clamp can be set to prevent the SR on time from going too long and causing shoot through. The minimum clamp can be set based on the light load condition where the desired SR turnoff edge offset is the maximum.
In addition to the SR adjustment accumulator clamps, the SR pulse falling edge is naturally clamped at 50% or 100% or the switching period in UCD3138A. This natural clamp is a default feature of UCD3138A and does not require any special setting.
The body diode must maintain a minimum conduction time for the UCD3138A DTC interface to function properly. The minimum body-diode conduction time is set by the DTC target and target register. A target hysteresis register can also be set to reduce the steady-state output-voltage ripple.
If the detected body-diode conduction time is less than the programmed threshold, negative current can occur. This threshold can be set by the fault threshold register in the UCD3138A DTC module. If a DTC fault is detected, the SR on time is reduced by a programed step size in the next switching cycle. This step size is defined by FLT_STEP register in the DTC module. To avoid noise and jitter in the negative current fault detection, a consecutive DTC fault counter can be used. A fault step is executed only after a consecutive number of faults are detected.
After all these registers are set, enable the UCD3138A DTC module in automatic control mode, enable the turnon-edge optimization on the UCD7138 device, and review the different operation conditions to see the overall system performance. The DTC module can be turned on or off by toggling DTC_EN bit in Loop Mux register in UCD3138A. The performance before and after SR optimization control can be compared very easily as shown in the Application Curves section.
No optimization, SR on time too long. | ||
High VDS stress on the other SR. | ||
Horizontal: 200 ns/div |
No optimization, SR on time too short. Low efficiency. | ||
Horizontal: 200 ns/div |
With optimization | ||
Horizontal: 200 ns/div | ||
With optimization | ||
Horizontal: 200 ns/div |
No optimization, SR on turnon too late. Low efficiency. | ||
Horizontal: 200 ns/div |
No optimization, SR turnon too early. | ||
Horizontal: 200 ns/div |
Efficiency increase at peak efficiency: 0.54% | Peak efficiency increase (occurs at no-load): 2.62% | ||
Average efficiency increase over constant voltage load range: 0.63% | |||
Peak efficiency with and without SR optimization: 94.85% at 19.92 A |
With optimization | ||
Horizontal: 200 ns/div |
With optimization | ||
Horizontal: 200 ns/div |