JAJSHD5D November   2010  – April  2019 UCD90160

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     簡略化されたアプリケーション回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: I2C/SMBus/PMBus
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail Configuration
      2. 8.3.2 TI Fusion GUI
      3. 8.3.3 PMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power-Supply Sequencing
        1. 8.4.1.1 Turn-on Sequencing
        2. 8.4.1.2 Turn-off Sequencing
        3. 8.4.1.3 Sequencing Configuration Options
      2. 8.4.2  Pin-Selected Rail States
      3. 8.4.3  Voltage Monitoring
      4. 8.4.4  Fault Responses and Alert Processing
      5. 8.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 8.4.6  GPIOs
      7. 8.4.7  GPO Control
      8. 8.4.8  GPO Dependencies
        1. 8.4.8.1 GPO Delays
        2. 8.4.8.2 State Machine Mode Enable
      9. 8.4.9  GPI Special Functions
      10. 8.4.10 Power-Supply Enables
      11. 8.4.11 Cascading Multiple Devices
      12. 8.4.12 PWM Outputs
        1. 8.4.12.1 FPWM1-8
        2. 8.4.12.2 PWM1-4
      13. 8.4.13 Programmable Multiphase PWMs
      14. 8.4.14 Margining
        1. 8.4.14.1 Open-Loop Margining
        2. 8.4.14.2 Closed-Loop Margining
      15. 8.4.15 System Reset Signal
      16. 8.4.16 Watch Dog Timer
      17. 8.4.17 Run Time Clock
      18. 8.4.18 Data and Error Logging to Flash Memory
      19. 8.4.19 Brownout Function
      20. 8.4.20 PMBus Address Selection
    5. 8.5 Programming
      1. 8.5.1 Device Configuration and Programming
        1. 8.5.1.1 Full Configuration Update While in Normal Mode
      2. 8.5.2 JTAG Interface
      3. 8.5.3 Internal Fault Management and Memory Error Correction (ECC)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Estimating ADC Reporting Accuracy
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
SUPPLY CURRENT
IV33A Supply current(1) VV33A = 3.3 V 8 mA
IV33DIO VV33DIO = 3.3 V 2 mA
IV33D VV33D = 3.3 V 40 mA
IV33D VV33D = 3.3 V, storing configuration parameters in flash memory 50 mA
ANALOG INPUTS (MON1–MON16)
VMON Input voltage range MON1–MON13 0 2.5 V
MON14–MON16 0.2 2.5 V
INL ADC integral nonlinearity –4 4 LSB
DNL ADC differential nonlinearity -2 2 LSB
Ilkg Input leakage current 3 V applied to pin 100 nA
IOFFSET Input offset current 1-kΩ source impedance –5 5 μA
RIN Input impedance MON1–MON13, ground reference 8 MΩ
MON14–MON16, ground reference 0.5 1.5 3 MΩ
CIN Input capacitance 10 pF
tCONVERT ADC sample period 16 voltages sampled, 3.89 μsec/sample 400 μsec
VREF ADC 2.5 V, internal reference accuracy 0°C to 125°C –0.5% 0.5%
–40°C to 125°C –1% 1%
ANALOG INPUT (PMBUS_ADDRx)
IBIAS Bias current for PMBus Addr pins 9 11 μA
VADDR_OPEN Voltage – open pin PMBUS_ADDR0, PMBUS_ADDR1 open 2.26 V
VADDR_SHORT Voltage – shorted pin PMBUS_ADDR0, PMBUS_ADDR1 short to ground 0.124 V
DIGITAL INPUTS AND OUTPUTS
VOL Low-level output voltage IOL = 6 mA(2), V33DIO = 3 V Dgnd + 0.25 V
VOH High-level output voltage IOH = –6 mA(3), V33DIO = 3 V V33DIO
– 0.6		 V
VIH High-level input voltage V33DIO = 3 V 2.1 3.6 V
VIL Low-level input voltage V33DIO = 3.5 V 1.4 V
MARGINING OUTPUTS
TPWM_FREQ MARGINING-PWM frequency FPWM1-8 15.260 125000 kHz
PWM3-4 0.001 7800
DUTYPWM MARGINING-PWM duty cycle range 0% 100%
SYSTEM PERFORMANCE
VDDSlew Minimum VDD slew rate VDD slew rate between 2.3 V and 2.9 V 0.25 V/ms
VRESET Supply voltage at which device comes out of reset For power-on reset (POR) 2.4 V
tRESET Low-pulse duration needed at RESET pin To reset device during normal operation 2 μS
f(PCLK) Internal oscillator frequency TA = 125°C, TA = 25°C 240 250 260 MHz
tretention Retention of configuration parameters TJ = 25°C 100 Years
Write_Cycles Number of nonvolatile erase/write cycles TJ = 25°C 20 K cycles
(1) Typical supply current values are based on device programmed but not configured, and no peripherals connected to any pins.
(2) The maximum total current, IOLmax, for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop specified.
(3) The maximum total current, IOHmax, for all outputs combined, should not exceed 48 mA to hold the maximum voltage drop specified.