JAJSFV7C September 2016 – March 2020 UCD90160A
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Typical values at TA = 25°C and VCC = 3.3 V (unless otherwise noted) | ||||||
fSMB | SMBus/PMBus operating frequency | Slave mode, SMBC 50% duty cycle | 10 | 400 | kHz | |
fI2C | I2C operating frequency | Slave mode, SCL 50% duty cycle | 10 | 400 | kHz | |
t(BUF) | Bus free time between start and stop | 1.3 | μs | |||
t(HD:STA) | Hold time after (repeated) start | 0.6 | μs | |||
t(SU:STA) | Repeated start setup time | 0.6 | μs | |||
t(SU:STO) | Stop setup time | 0.6 | μs | |||
t(HD:DAT) | Data hold time | Receive mode | 0 | ns | ||
t(SU:DAT) | Data setup time | 100 | ns | |||
t(TIMEOUT) | Error signal/detect | See (1) | 35 | ms | ||
t(LOW) | Clock low period | 1.3 | μs | |||
t(HIGH) | Clock high period | See (2) | 0.6 | μs | ||
t(LOW:SEXT) | Cumulative clock low slave extend time | See (3) | 25 | ms | ||
tf | Clock/data fall time | Fall time tf = 0.9 VDD to (VILmax – 0.15) | 20 + 0.1 Cb(4) | 300 | ns | |
tr | Clock/data rise time | Rise time tr = (VILmax – 0.15) to (VIHmin + 0.15) | 20 + 0.1 Cb(4) | 300 | ns | |
Cb | Total capacitance of one bus line | 400 | pF |