JAJSFV7C September   2016  – March 2020 UCD90160A

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Rail Configuration
      2. 8.3.2 TI Fusion GUI
      3. 8.3.3 PMBus Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Supply Sequencing
        1. 8.4.1.1 Turn-on Sequencing
        2. 8.4.1.2 Turn-off Sequencing
        3. 8.4.1.3 Sequencing Configuration Options
      2. 8.4.2  Pin-Selected Rail States
      3. 8.4.3  Voltage Monitoring
      4. 8.4.4  Fault Responses and Alert Processing
      5. 8.4.5  Shut Down All Rails and Sequence On (Resequence)
      6. 8.4.6  GPIOs
      7. 8.4.7  GPO Control
      8. 8.4.8  GPO Dependencies
        1. 8.4.8.1 GPO Delays
        2. 8.4.8.2 State Machine Mode Enable
      9. 8.4.9  GPI Special Functions
        1. 8.4.9.1 Fault Shutdown Rails
        2. 8.4.9.2 Configured as Sequencing Debug Pin
        3. 8.4.9.3 Configured as Fault Pin
        4. 8.4.9.4 Cold Boot Mode Enable
      10. 8.4.10 Power Supply Enables
      11. 8.4.11 Cascading Multiple Devices
      12. 8.4.12 PWM Outputs
        1. 8.4.12.1 FPWM1-8
        2. 8.4.12.2 PWM1-4
      13. 8.4.13 Programmable Multiphase PWMs
      14. 8.4.14 Margining
        1. 8.4.14.1 Open-Loop Margining
        2. 8.4.14.2 Closed-Loop Margining
      15. 8.4.15 System Reset Signal
      16. 8.4.16 Watch Dog Timer
      17. 8.4.17 Run Time Clock
      18. 8.4.18 Data and Error Logging to Flash Memory
      19. 8.4.19 Brownout Function
      20. 8.4.20 PMBus Address Selection
      21. 8.4.21 Device Reset
    5. 8.5 Programming
      1. 8.5.1 Device Configuration and Programming
        1. 8.5.1.1 Full Configuration Update While in Normal Mode
      2. 8.5.2 JTAG Interface
      3. 8.5.3 Internal Fault Management and Memory Error Correction (ECC)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
      4. 9.2.4 Estimating ADC Reporting Accuracy
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

UCD90160A pinout_grouped_slvsdd4.gif
RGC Package
64-Pin VQFN
Top View

Pin Functions(1)

PIN I/O DESCRIPTION
NAME NO.
ANALOG MONITOR INPUTS
MON1 1 I Analog input (0 to 2.5 V)
MON2 2 I Analog input (0 to 2.5 V)
MON3 3 I Analog input (0 to 2.5 V)
MON4 4 I Analog input (0 to 2.5 V)
MON5 5 I Analog input (0 to 2.5 V)
MON6 6 I Analog input (0 to 2.5 V)
MON7 55 I Analog input (0 to 2.5 V)
MON8 56 I Analog input (0 to 2.5 V)
MON9 57 I Analog input (0 to 2.5 V)
MON10 58 I Analog input (0 to 2.5 V)
MON11 59 I Analog input (0 to 2.5 V)
MON12 62 I Analog input (0 to 2.5 V)
MON13 63 I Analog input (0 to 2.5 V)
MON14 50 I Analog input (0.2 to 2.5 V)
MON15 52 I Analog input (0.2 to 2.5 V)
MON16 54 I Analog input (0.2 to 2.5 V)
GENERAL-PURPOSE INPUT AND OUTPUT
GPIO1 11 I/O General-purpose discrete I/O
GPIO2 12 I/O General-purpose discrete I/O
GPIO3 13 I/O General-purpose discrete I/O
GPIO4 14 I/O General-purpose discrete I/O
GPIO13 25 I/O General-purpose discrete I/O
GPIO14 29 I/O General-purpose discrete I/O
GPIO15 30 I/O General-purpose discrete I/O
GPIO16 33 I/O General-purpose discrete I/O
GPIO17 34 I/O General-purpose discrete I/O
GPIO18 35 I/O General-purpose discrete I/O
PWM OUTPUTS
FPWM1/GPIO5 17 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM2/GPIO6 18 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM3/GPIO7 19 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM4/GPIO8 20 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM5/GPIO9 21 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM6/GPIO10 22 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM7/GPIO11 23 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
FPWM8/GPIO12 24 I/O/PWM PWM (15.259 kHz to 125 MHz) or GPIO
PWM1/GPI1 31 I/PWM Fixed 10-kHz PWM output or GPI
PWM2/GPI2 32 I/PWM Fixed 1-kHz PWM output or GPI
PWM3/GPI3 42 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI
PWM4/GPI4 41 I/PWM PWM (0.93 Hz to 7.8125 MHz) or GPI
PMBus COMM INTERFACE
PMBUS_CLK 15 I/O PMBus clock (must have pullup to 3.3 V)
PMBUS_DATA 16 I/O PMBus data (must have pullup to 3.3 V)
PMBALERT 27 O PMBus alert, active-low, open-drain output (must have pullup to 3.3 V)
PMBUS_CNTRL 28 I PMBus control
PMBUS_ADDR0 61 I PMBus analog address input. Least-significant address bit
PMBUS_ADDR1 60 I PMBus analog address input. Most-significant address bit
JTAG
TRCK 10 O Test return clock
TCK/GPIO19 36 I/O Test clock or GPIO
TDO/GPIO20 37 I/O Test data out or GPIO
TDI/GPIO21 38 I/O Test data in (tie to VDD with 10-kΩ resistor) or GPIO
TMS/GPIO22 39 I/O Test mode select (tie to VDD with 10-kΩ resistor) or GPIO
TRST 40 I Test reset. Tie to ground with 10-kΩ resistor
INPUT POWER AND GROUNDS
RESET 9 Active-low device reset input. Hold low for at least 2 μs to reset the device. Refer to the Device Reset section.
V33A 46 Analog 3.3-V supply. Refer to the Layout Guidelines section.
V33D 45 Digital core 3.3-V supply. Refer to the Layout Guidelines section.
V33DIO1 7 Digital I/O 3.3-V supply. Refer to the Layout Guidelines section.
V33DIO2 44 Digital I/O 3.3-V supply. Refer to the Layout Guidelines section.
BPCap 47 1.8-V bypass capacitor. Refer to the Layout Guidelines section.
AVSS1 49 Analog ground
AVSS2 48 Analog ground
AVSS3 64 Analog ground
DVSS1 8 Digital ground
DVSS2 26 Digital ground
DVSS3 43 Digital ground
NC1 51 No Connect
NC2 53 No Connect
QFP ground pad NA Thermal pad – tie to ground plane.
(1) The maximum number of configurable rails is 16. The maximum number of configurable GPIs is 8. The maximum number of configurable Boolean Logic GPOs is 16.