JAJSHD6B August   2016  – May  2019 UCD90320

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Non-Volatile Memory Characteristics
    7. 7.7 I2C/PMBus Interface Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TI Fusion Digital Power Designer software
      2. 8.3.2 PMBUS Interface
      3. 8.3.3 Rail Setup
    4. 8.4 Device Functional Modes
      1. 8.4.1  Rail Monitoring Configuration
      2. 8.4.2  GPI Configuration
      3. 8.4.3  Rail Sequence Configuration
      4. 8.4.4  Fault Responses Configuration
      5. 8.4.5  GPO Configuration
        1. 8.4.5.1 Command Controlled GPO
        2. 8.4.5.2 Logic GPO
      6. 8.4.6  Margining Configuration
      7. 8.4.7  Pin Selected Rail States Configuration
      8. 8.4.8  Watchdog Timer
      9. 8.4.9  System Reset Function
      10. 8.4.10 Cascading Multiple Devices
      11. 8.4.11 Rail Monitoring
      12. 8.4.12 Status Monitoring
      13. 8.4.13 Data and Error Logging to EEPROM Memory
      14. 8.4.14 Black Box First Fault Logging
      15. 8.4.15 PMBus Address Selection
      16. 8.4.16 ADC Reference
      17. 8.4.17 Device Reset
      18. 8.4.18 Brownout
      19. 8.4.19 Internal Fault Management
    5. 8.5 Device Configuration and Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 コミュニティ・リソース
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IV33 Supply Current VV33D = VV33A = 3.3 V 31.4 54.9 mA
ON-CHIP LOW DROP-OUT (LDO) REGULATOR
CLDO External filter capacitor size for internal power supply(1) 2.5 4 µF
VLDO LDO output voltage 1.08 1.2 1.32 V
IINRUSH Inrush current 50 250 mA
ANALOG-TO-DIGITAL CONVERTER (ADC)(2)(3)
V33A ADC supply voltage 2.97 3.3 3.63 V
AVSS ADC ground voltage 0 V
CV33A Voltage reference decoupling capacitance between V33A and AVSS (if using internal reference) (4) 1.01 µF
VREFA+ Positive external voltage reference on VREFA+ pin 2.4 3 V
VREF– Negative external voltage reference on VREF– pin VAVSS AVSS 0.3 V
IREF Current on VREF+ pin input External VREF+ = 3.3 V 330.5 440 µA
CREF Voltage reference decoupling capacitance between VREFA+ and VREFA– (if using external reference)(4) 1.01 µF
VADCIN Analog input range, internal reference(5) 0 V33A V
Analog input range, external reference(6) VVREFA– VVREFA+
IL ADC input leakage current 2 µA
RADC ADC equivalent input resistance 2.5 kΩ
CADC ADC equivalent input capacitance 10 pF
FCONV ADC conversion rate (on each ADC channel)(1) 1 MSPS
N ADC resolution 12 bits
ET Total unadjusted error, over full input rangea when using internal reference ±10 ±30 LSB
Total unadjusted error, over full input range when using external reference ±2.5 ±4
DIGITAL INPUTS AND OUTPUTS (GPIO, Logic GPO, EN, AND MARGIN PINS)
VIH I/O high-level input voltage(7) 0.65 × VV33D 5.5 V
VIL I/O low-level input voltage 0 0.35 × VV33D V
VHYS I/O input hysteresis 0.2 V
VOH I/O high-level output voltage 2.4 V
VOL I/O low-level output voltage 0.4 V
IOH High-level source current VOH = 2.4 V(8) 4 mA
IOL Low-level sink current VOL = 0.4 V(8) 4 mA
RESET AND BROWNOUT
V33DSlew Minimum V33D slew rate between 2.8 V and 3.2 V 0.1 V/ms
VRESET Supply voltage at which device comes out of reset 2 2.3 2.6 V
VBOR Supply voltage at which device enters brownout 2.93 3.02 3.11 V
VSHDN Supply voltage at which device shuts down 2.7 2.78 2.87 V
tRESET Minimum low-pulse width needed at RESET̅ pin 250 ns
tIRT Internal reset time(9) 9 11.5 ms
(1) Connect the capacitor as close as possible to pin D6.
(2) Total of two ADC channels run independently during normal operation.
(3) Total unadjusted error is the maximum error at any one code versus the ideal ADC curve. It includes offset error, gain error, and INL at any given ADC code.
(4) Two capacitors (1.0 µF and 0.01 µF) connected in parallel.
(5) Internal reference is connected directly between V33A and AVSS.
(6) External reference noise level must be under 12 bit (–74 dB) of full scale input, over input bandwidth, measured at VREFA+ - VREFA–.
(7) PMBUS_CNTRL, PMBALERT, MARGIN19 and MARGIN20 pins have VV33D + 0.3 V as maximum input voltage rating.
(8) IO specifications reflect the maximum current where the corresponding output voltage meets the VOH/VOL thresholds.
(9) If power-loss or brown-out event occurs during an EEPROM program or erase operation, and EEPROM needs to be repaired (which is a rare case), the internal reset time may be longer.