JAJSHD6B August   2016  – May  2019 UCD90320

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     アプリケーション概略図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Non-Volatile Memory Characteristics
    7. 7.7 I2C/PMBus Interface Timing Requirements
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TI Fusion Digital Power Designer software
      2. 8.3.2 PMBUS Interface
      3. 8.3.3 Rail Setup
    4. 8.4 Device Functional Modes
      1. 8.4.1  Rail Monitoring Configuration
      2. 8.4.2  GPI Configuration
      3. 8.4.3  Rail Sequence Configuration
      4. 8.4.4  Fault Responses Configuration
      5. 8.4.5  GPO Configuration
        1. 8.4.5.1 Command Controlled GPO
        2. 8.4.5.2 Logic GPO
      6. 8.4.6  Margining Configuration
      7. 8.4.7  Pin Selected Rail States Configuration
      8. 8.4.8  Watchdog Timer
      9. 8.4.9  System Reset Function
      10. 8.4.10 Cascading Multiple Devices
      11. 8.4.11 Rail Monitoring
      12. 8.4.12 Status Monitoring
      13. 8.4.13 Data and Error Logging to EEPROM Memory
      14. 8.4.14 Black Box First Fault Logging
      15. 8.4.15 PMBus Address Selection
      16. 8.4.16 ADC Reference
      17. 8.4.17 Device Reset
      18. 8.4.18 Brownout
      19. 8.4.19 Internal Fault Management
    5. 8.5 Device Configuration and Programming
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 コミュニティ・リソース
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 商標
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.7 I2C/PMBus Interface Timing Requirements

MIN NOM MAX UNIT
I1 t(HD:STA) Start condition hold time 450 ns
I2 t(LOW) Clock low period(1) 450 ns
I3 tr Clock rise time and data rise time(2) See(2) ns
I4 t(HD:DAT) Data hold time 25 ns
I5 tf Clock fall time and data fall time(3) 112.5 125 ns
I6 t(HIGH) Clock high time 300 ns
I7 t(SU:DAT) Data setup time 225 ns
I8 t(SU:STA) Start condition setup time (repeated start only) 450 ns
I9 t(SU:STO) Stop condition setup time 300 ns
I10 t(DV) Data valid 25 ns
(1) PMBus host must support clock stretching per PMBus Power System Management Protocol Specification Part I General Requirements, Transport and Electrical Interface, Revision 1.2, Section 5.2.6.
(2) Because the I2CSCL signal and the I2CSDA signal operate as open-drain-type signals, which the controller can actively drive only "Low", the time that either signal takes to reach a high level depends on external signal capacitance and pull-up resistor values.
(3) Specified at a nominal 50-pF load.
UCD90320 LMI_I2C_timing_SLVSCW0.gifFigure 1. I2C/PMBus Timing Diagram