9.1.1 Considerations for MONX Input Series Resistance, R_S

R_S is the series impedance between the sampled voltage source (low impedance power supply output) and the UCD9081 MONx input pin. This resistance can affect UCD9081 sampling accuracy if it is too large. In most cases (when the power supply being monitored has a lower VOUT than the UCD9081 voltage reference being used) this resistance is low and can be ignored. In cases where a voltage divider is used to scale the monitored voltage below the voltage reference, the impedance of this network must be chosen so that it does not adversely affect the analog to digital converter (ADC) conversion accuracy. The equivalent series impedance (R_S) of the divider network is just the parallel combination of the pullup and pulldown resistors.

The UCD9081 has an internal clock (DCO) whose frequency is set by ROSC on pin 32. The DCO frequency can be affected by several factors including supply voltage and temperature. This clock is used by the ADC to set up an ADC sample or gate time (T_GATE) at each MONx pin. The voltage sampled must be allowed to settle sufficiently during T_GATE. The settling time is affected by the UCD9081 internal capacitance and R_S. To allow for sufficient settling time over DCO frequency, supply voltage, and temperature variation, choose R_S < 6 kΩ.

9.1.2 Estimating UCD9081 Reporting Accuracy Over Variations in ADC Voltage Reference

The UCD9081 uses a 10-bit ADC. The ADC in the UCD9081 derives its reference voltage (V_R+ ) from either the external (V_CC pin) or internal (V_REF+) reference voltage to scale the digitally reported voltage. The least significant bit (LSB) voltage value is V_LSB = V_R+/2ⁿ where n = 10 and V_R+ is the reference voltage used (either external V_CC = 3.3 V nominal, or internal V_REF+ = 2.5 V nominal). For external V_R+ = V_CC = 3.3 V, V_LSB = 3.3 / 1024 = 3.22 mV and for internal V_R+ = V_REF+ = 2.5 V, V_LSB = 2.5 / 1024 = 2.44 mV.

The error in the reported voltage is a function of the ADC linearity error(s) as well as variations in the ADC reference voltage. The total unadjusted error (E_TUE) for the ADC in the UCD9081 is ±5 LSB and the variation of the internal 2.5-V reference is ±6% maximum. V_TUE is calculated as V_LSB × E_TUE for the particular reference voltage used. The reported voltage error is the sum of the reference voltage error and the ADC total unadjusted error. At lower monitored voltages, E_TUE may dominate reported error while at higher monitored voltages V_R+ dominates the reported error. Reported error (percent) can be calculated using Equation 3.

Listed below are four examples using Equation 3 to estimate reported error:

• V_R+ = 2.5 V, REFTOL = 6%, V_ACT = 0.25 V, RPT_ERR = 11.2%
• V_R+ = 2.5 V, REFTOL = 6%, V_ACT = 2.25 V, RPT_ERR = 6.6%
• V_R+ = 3.3 V, REFTOL = 1%, V_ACT = 0.25 V, RPT_ERR = 7.5%
• V_R+ = 3.3 V, REFTOL = 1%, V_ACT = 2.25 V, RPT_ERR = 1.7%

In addition to the reporting errors due to ADC and voltage reference, there can be additional errors due to divider resistor tolerance when monitoring voltages higher than V_R+. These errors can be added to the reporting error described above.

9.2.1 Design Requirements

RST pin must have a 10-kΩ pullup resistor to 3.3 V and 10-nF decoupling capacitor to ground. The component must be placed as close to the RST pin as possible.

9.2.2 Detailed Design Procedure

UCD9081 GUI can be used to design the device configuration. An USB-to-I²C Adapter from Texas Instruments can be used to connect GUI to I²C.

General design steps include:

1. General rail setup
2. Rail sequencing conditions setup
3. Alarm action (fault response) setup
4. System conditions setup
5. General GPO setup
6. GPO sequence setup

After configuration changes, click Store to Buffer to save the current entries to a GUI. Click Update Parameters and Sequence to permanently store the new configuration into the device data flash.

9.2.3 Application Curve

Figure 21. Example Power-On Sequence