The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run protocol is enabled, the bridge assumes the role of the central resource master.
To enable the clock run function, terminal CLKRUN_EN is asserted high. Then, terminal GPIO0 is enabled as the
CLKRUN signal. An external pullup resistor must be provided to prevent the
CLKRUN signal from floating To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock run status register at offset DAh (see Section 8.4.69) is read.
Since the bridge has several unique features associated with the PCI bus interface, the system designer must consider the following interdependencies between these features and the
CLKRUN feature:
- If the system designer chooses to generate the PCI bus clock externally, then the
CLKRUN mode of the bridge must be disabled. The central resource function within the bridge only operates as a
CLKRUN master and does not support the
CLKRUN slave mode.
- If the central resource function has stopped the PCI bus clocks, then the bridge still detects
INTx state changes and will generate and send PCI Express messages upstream.
- If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks, then any PCI bus device that needs to report an IRQ interrupt asserts
CLKRUN to start the bus clocks.
- When a PCI bus device asserts
CLKRUN, the central resource function turns on PCI bus clocks for a minimum of 512 cycles.
- If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus clocks running until the IRQ interrupt is cleared by software.
- If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream transaction that is forwarded to the PCI bus interface, then the bridge asserts
CLKRUN to start the bus clocks.
- The central resource function is reset by PCI bus reset (
PRST) assuring that clocks are present during PCI bus resets.