JAJSQ97 データシート

JAJSQ97J may 2009 – january 2021 XIO2001

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PNP|128
- MPQF060E
ZWS|169
- MPBGAK4B
ZAJ|144
- MPBG878A

サーマルパッド・メカニカル・データ

PNP|128
- PPTD154D

発注情報

8.3.2.3 Reference Clock

The XIO2001 requires an external reference clock for the PCI-Express interface. The section provide information concerning the requirements for this reference clock. The XIO2001 is designed to meet all stated specifications when the reference clock input is within all PCI Express operating parameters. This includes both standard clock oscillator sources or spread spectrum clock oscillator sources.

The XIO2001 supports two options for the PCI Express reference clock: a 100-MHz common differential reference clock or a 125-MHz asynchronous single-ended reference clock. Both implementations are described below.

The first option is a system-wide, 100-MHz differential reference clock. A single clock source with multiple differential clock outputs is connected to all PCI Express devices in the system. The differential connection between the clock source and each PCI Express device is point-topoint. This system implementation is referred to as a common clock design.

The XIO2001 is optimized for this type of system clock design. The REFCLK+ and REFCLK– pins provide differential reference clock inputs to the XIO2001. The circuit board routing rules associated with the 100-MHz differential reference clock are the same as the 2.5-Gb/s TX and RX link routing rules itemized in Section 8.3.2.1. The only difference is that the differential reference clock does not require series capacitors. The requirement is a DC connection from the clock driver output to the XIO2001 receiver input.

Terminating the differential clock signal is circuit board design specific. But, the XIO2001 design has no internal 50- Ω -to-ground termination resistors. Both REFCLK inputs, at approximately 20 k Ω to ground, are high-impedance inputs.

The second option is a 125-MHz asynchronous single-ended reference clock. For this case, the devices at each end of the PCI Express link have different clock sources. The XIO2001 has a 125-MHz single-ended reference clock option for asynchronous clocking designs. When the REFCLK125_SEL input terminal is tied to V_{DD_33}, this clocking mode is enabled.

The single-ended reference clock is attached to the REFCLK+ terminal. The REFCLK+ input, at approximately 20 k Ω , is a high-impedance input. Any clock termination design must account for a high- impedance input. The REFCLK– pin is attached to a 0.1- μ F capacitor. The capacitor’s second pin is connected to V_SSA.