JAJSQ97J may   2009  – january 2021 XIO2001

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
    1.     Pin Assignments
    2.     Pin Descriptions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information #GUID-4E9F689A-942D-492C-8F28-F3CC5F1BD0E6/SCPS2129637AN1
    5. 6.5  Nominal Power Consumption
    6. 6.6  PCI Express Differential Transmitter Output Ranges
    7. 6.7  PCI Express Differential Receiver Input Ranges
    8. 6.8  PCI Express Differential Reference Clock Input Ranges #GUID-60875016-888B-4DD4-A309-543B497BAC9F/SCPS1718455
    9. 6.9  PCI Bus Electrical Characteristics
    10. 6.10 3.3-V I/O Electrical Characteristics
    11. 6.11 PCI Bus Timing Requirements
    12. 6.12 Power-Up/-Down Sequencing
      1. 6.12.1 Power-Up Sequence
      2. 6.12.2 Power-Down Sequence
  8. Parameter Measurement Information
    1.     25
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bridge Reset Features
      2. 8.3.2  PCI Express Interface
        1. 8.3.2.1 2.5-Gb/s Transmit and Receive Links
        2. 8.3.2.2 Transmitter Reference Resistor
        3. 8.3.2.3 Reference Clock
        4. 8.3.2.4 Reset
        5. 8.3.2.5 Beacon
        6. 8.3.2.6 Wake
        7. 8.3.2.7 Initial Flow Control Credits
        8. 8.3.2.8 PCI Express Message Transactions
      3. 8.3.3  PCI Port Arbitration
        1. 8.3.3.1 Classic PCI Arbiter
      4. 8.3.4  Configuration Register Translation
      5. 8.3.5  PCI Interrupt Conversion to PCI Express Messages
      6. 8.3.6  PME Conversion to PCI Express Messages
      7. 8.3.7  PCI Express to PCI Bus Lock Conversion
      8. 8.3.8  Two-Wire Serial-Bus Interface
        1. 8.3.8.1 Serial-Bus Interface Implementation
        2. 8.3.8.2 Serial-Bus Interface Protocol
        3. 8.3.8.3 Serial-Bus EEPROM Application
        4. 8.3.8.4 Accessing Serial-Bus Devices Through Software
      9. 8.3.9  Advanced Error Reporting Registers
      10. 8.3.10 Data Error Forwarding Capability
      11. 8.3.11 General-Purpose I/O Interface
      12. 8.3.12 Set Slot Power Limit Functionality
      13. 8.3.13 PCI Express and PCI Bus Power Management
      14. 8.3.14 Auto Pre-Fetch Agent
    4. 8.4 Register Maps
      1. 8.4.1  Classic PCI Configuration Space
      2. 8.4.2  Vendor ID Register
      3. 8.4.3  Device ID Register
      4. 8.4.4  Command Register
      5. 8.4.5  Status Register
      6. 8.4.6  Class Code and Revision ID Register
      7. 8.4.7  Cache Line Size Register
      8. 8.4.8  Primary Latency Timer Register
      9. 8.4.9  Header Type Register
      10. 8.4.10 BIST Register
      11. 8.4.11 Device Control Base Address Register
      12. 8.4.12 Primary Bus Number Register
      13. 8.4.13 Secondary Bus Number Register
      14. 8.4.14 Subordinate Bus Number Register
      15. 8.4.15 Secondary Latency Timer Register
      16. 8.4.16 I/O Base Register
      17. 8.4.17 I/O Limit Register
      18. 8.4.18 Secondary Status Register
      19. 8.4.19 Memory Base Register
      20. 8.4.20 Memory Limit Register
      21. 8.4.21 Prefetchable Memory Base Register
      22. 8.4.22 Prefetchable Memory Limit Register
      23. 8.4.23 Prefetchable Base Upper 32-Bit Register
      24. 8.4.24 Prefetchable Limit Upper 32-Bit Register
      25. 8.4.25 I/O Base Upper 16-Bit Register
      26. 8.4.26 I/O Limit Upper 16-Bit Register
      27. 8.4.27 Capabilities Pointer Register
      28. 8.4.28 Interrupt Line Register
      29. 8.4.29 Interrupt Pin Register
      30. 8.4.30 Bridge Control Register
      31. 8.4.31 Capability ID Register
      32. 8.4.32 Next Item Pointer Register
      33. 8.4.33 Subsystem Vendor ID Register
      34. 8.4.34 Subsystem ID Register
      35. 8.4.35 Capability ID Register
      36. 8.4.36 Next Item Pointer Register
      37. 8.4.37 Power Management Capabilities Register
      38. 8.4.38 Power Management Control/Status Register
      39. 8.4.39 Power Management Bridge Support Extension Register
      40. 8.4.40 Power Management Data Register
      41. 8.4.41 MSI Capability ID Register
      42. 8.4.42 Next Item Pointer Register
      43. 8.4.43 MSI Message Control Register
      44. 8.4.44 MSI Message Lower Address Register
      45. 8.4.45 MSI Message Upper Address Register
      46. 8.4.46 MSI Message Data Register
      47. 8.4.47 PCI Express Capability ID Register
      48. 8.4.48 Next Item Pointer Register
      49. 8.4.49 PCI Express Capabilities Register
      50. 8.4.50 Device Capabilities Register
      51. 8.4.51 Device Control Register
      52. 8.4.52 Device Status Register
      53. 8.4.53 Link Capabilities Register
      54. 8.4.54 Link Control Register
      55. 8.4.55 Link Status Register
      56. 8.4.56 Serial-Bus Data Register
      57. 8.4.57 Serial-Bus Word Address Register
      58. 8.4.58 Serial-Bus Slave Address Register
      59. 8.4.59 Serial-Bus Control and Status Register
      60. 8.4.60 GPIO Control Register
      61. 8.4.61 GPIO Data Register
      62. 8.4.62 TL Control and Diagnostic Register 0
      63. 8.4.63 Control and Diagnostic Register 1
      64. 8.4.64 Control and Diagnostic Register 2
      65. 8.4.65 Subsystem Access Register
      66. 8.4.66 General Control Register
      67. 8.4.67 Clock Control Register
      68. 8.4.68 Clock Mask Register
      69. 8.4.69 Clock Run Status Register
      70. 8.4.70 Arbiter Control Register
      71. 8.4.71 Arbiter Request Mask Register
      72. 8.4.72 Arbiter Time-Out Status Register
      73. 8.4.73 Serial IRQ Mode Control Register
      74. 8.4.74 Serial IRQ Edge Control Register
      75. 8.4.75 Serial IRQ Status Register
      76. 8.4.76 Pre-Fetch Agent Request Limits Register
      77. 8.4.77 Cache Timer Transfer Limit Register
      78. 8.4.78 Cache Timer Lower Limit Register
      79. 8.4.79 Cache Timer Upper Limit Register
    5. 8.5 PCI Express Extended Configuration Space
      1. 8.5.1  Advanced Error Reporting Capability ID Register
      2. 8.5.2  Next Capability Offset/Capability Version Register
      3. 8.5.3  Uncorrectable Error Status Register
      4. 8.5.4  Uncorrectable Error Mask Register
      5. 8.5.5  Uncorrectable Error Severity Register
      6. 8.5.6  Correctable Error Status Register
      7. 8.5.7  Correctable Error Mask Register
      8. 8.5.8  Advanced Error Capabilities and Control Register
      9. 8.5.9  Header Log Register
      10. 8.5.10 Secondary Uncorrectable Error Status Register
      11. 8.5.11 Secondary Uncorrectable Error Severity
      12. 8.5.12 Secondary Error Capabilities and Control Register
      13. 8.5.13 Secondary Header Log Register
    6. 8.6 Memory-Mapped TI Proprietary Register Space
      1. 8.6.1  Device Control Map ID Register
      2. 8.6.2  Revision ID Register
      3. 8.6.3  GPIO Control Register
      4. 8.6.4  GPIO Data Register
      5. 8.6.5  Serial-Bus Data Register
      6. 8.6.6  Serial-Bus Word Address Register
      7. 8.6.7  Serial-Bus Slave Address Register
      8. 8.6.8  Serial-Bus Control and Status Register
      9. 8.6.9  Serial IRQ Mode Control Register
      10. 8.6.10 Serial IRQ Edge Control Register
      11. 8.6.11 Serial IRQ Status Register
      12. 8.6.12 Pre-Fetch Agent Request Limits Register
      13. 8.6.13 Cache Timer Transfer Limit Register
      14. 8.6.14 Cache Timer Lower Limit Register
      15. 8.6.15 Cache Timer Upper Limit Register
  10. Application, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 In-Card Implementation
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 VCCP Clamping Rail
          2. 9.2.1.1.2 Combined Power Outputs
          3. 9.2.1.1.3 Auxiliary Power
          4. 9.2.1.1.4 VSS and VSSA Pins
          5. 9.2.1.1.5 Capacitor Selection Recommendations
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 PCI Bus Interface
            1. 9.2.1.2.1.1 Bus Parking
            2. 9.2.1.2.1.2 I/O Characteristics
            3. 9.2.1.2.1.3 Clamping Voltage
            4. 9.2.1.2.1.4 PCI Bus Clock Run
            5. 9.2.1.2.1.5 PCI Bus External Arbiter
            6. 9.2.1.2.1.6 MSI Messages Generated from the Serial IRQ Interface
            7. 9.2.1.2.1.7 PCI Bus Clocks
      2. 9.2.2 External EEPROM
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 JTAG Interface
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 Combined Power
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 Power Filtering
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 1.5-V and 3.3-V Digital Supplies
      2. 9.4.2 1.5-V and 3.3-V Analog Supplies
      3. 9.4.3 1.5-V PLL Supply
      4. 9.4.4 Power-Up/Down Sequencing
      5. 9.4.5 Power Supply Filtering Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documents Conventions
      1. 10.1.1 XIO2001 Definition
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documents
        1. 10.2.1.1 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

2.5-Gb/s Transmit and Receive Links

The XIO2001 TX and RX terminals attach to the upstream PCI Express device over a 2.5-Gb/s high- speed differential transmit and receive PCI Express × 1 Link. The connection details are provided in Table 8-2.

Table 8-2 XIO2001/PCI Express Device Pin Connection Details
PIN NAMECOMMENTS
XIO2001UPSTREAM PCI EXPRESS DEVICE
TXPRXPXIO2001's transmit positive differential pin connects to the upstream device's receive positive differential pin.
TXNRXNXIO2001's transmit positive differential pin connects to the upstream device's receive negative differential pin.
RXPTXPXIO2001's transmit positive differential pin connects to the upstream device's receive positive differential pin.
RXNTXNXIO2001's transmit positive differential pin connects to the upstream device's receive negative differential pin.

The XIO2001 TXP and TXN terminals comprise a low-voltage, 100- Ω differentially driven signal pair. The RXP and RXN terminals for the XIO2001 receive a low-voltage, 100- Ω differentially driven signal pair. The XIO2001 has integrated 50- Ω termination resistors to VSS on both the RXP and RXN terminals eliminating the need for external components.

Each lane of the differential signal pair must be ac-coupled. The recommended value for the series capacitor is 0.1 μF. To minimize stray capacitance associated with the series capacitor circuit board solder pads, 0402-sized capacitors are recommended.

When routing a 2.5-Gb/s low-voltage, 100- Ω differentially driven signal pair, the following circuit board design guidelines must be considered:

  1. The PCI-Express drivers and receivers are designed to operate with adequate bit error rate margins over a 20 ” maximum length signal pair routed through FR4 circuit board material.
  2. Each differential signal pair must be 100- Ω differential impedance with each single-ended lane measuring in the range of 50 Ω to 55 Ω impedance to ground.
  3. The differential signal trace lengths associated with a PCI Express high-speed link must be length matched to minimize signal jitter. This length matching requirement applies only to the P and N signals within a differential pair. The transmitter differential pair does not need to be length matched to the receiver differential pair. The absolute maximum trace length difference between the TXP signal and TXN signal must be less than 5 mils. This also applies to the RXP and RXN signal pair.
  4. If a differential signal pair is broken into segments by vias, series capacitors, or connectors, the length of the positive signal trace must be length matched to the negative signal trace for each segment. Trace length differences over all segments are additive and must be less than 5 mils.
  5. The location of the series capacitors is critical. For add-in cards, the series capacitors are located between the TXP/TXN terminals and the PCI-Express connector. In addition, the capacitors are placed near the PCI Express connector. This translates to two capacitors on the motherboard for the downstream link and two capacitors on the add-in card for the upstream link. If both the upstream device and the downstream device reside on the same circuit board, the capacitors are located near the TXP/TXN terminals for each link.
  6. The number of vias must be minimized. Each signal trace via reduces the maximum trace length by approximately 2 inches. For example: if 6 vias are needed, the maximum trace length is 8 inches.
  7. When routing a differential signal pair, 45 degree angles are preferred over 90 degree angles. Signal trace length matching is easier with 45-degree angles and overall signal trace length is reduced.
  8. The differential signal pairs must not be routed over gaps in the power planes or ground planes. This causes impedance mismatches.
  9. If vias are used to change from one signal layer to another signal layer, it is important to maintain the same 50- Ω impedance reference to the ground plane. Changing reference planes causes signal trace impedance mismatches. If changing reference planes cannot be prevented, bypass capacitors connecting the two reference planes next to the signal trace vias will help reduce the impedance mismatch.
  10. If possible, the differential signal pairs must be routed on the top and bottom layers of a circuit board. Signal propagation speeds are faster on external signal layers.