JAJSQ97 データシート

JAJSQ97J may 2009 – january 2021 XIO2001

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PNP|128
- MPQF060E
ZWS|169
- MPBGAK4B
ZAJ|144
- MPBG878A

サーマルパッド・メカニカル・データ

PNP|128
- PPTD154D

発注情報

8.3.1 Bridge Reset Features

There are five bridge reset options that include internally-generated power-on reset, resets generated by asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot reset or setting a configuration register bit. Table 8-1 identifies these reset sources and describes how the bridge responds to each reset.

Table 8-1 XIO2001 Reset Options

RESET OPTION	XIO2001 FEATURE	RESET RESPONSE
Bridge internally-generated power-on reset	During a power-on cycle, the bridge asserts an internal reset and monitors the V_{DD_15_COMB} terminal. When this terminal reaches 90% of the nominal input voltage specification, power is considered stable. After stable power, the bridge monitors the PCI Express reference clock (REFCLK) and waits 10 μs after active clocks are detected. Then, internal power-on reset is deasserted.	When the internal power-on reset is asserted, all control registers, state machines, sticky register bits, and power management state machines are initialized to their default state. In addition, the XIO2001 asserts the internal PCI bus reset.
Global reset input GRST	When GRST is asserted low, an internal power-on reset occurs. This reset is asynchronous and functions during both normal power states and V_AUX power states.	When GRST is asserted low, all control registers, state machines, sticky register bits, and power management state machines are initialized to their default state. In addition, the bridge asserts PCI bus reset ( PRST). When the rising edge of GRST occurs, the bridge samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The bridge starts link training within 80 ms after GRST is deasserted.
PCI Express reset input PERST	This XIO2001 input terminal is used by an upstream PCI Express device to generate a PCI Express reset and to signal a system power good condition.	When PERST is asserted low, all control register bits that are not sticky are reset. Within the configuration register maps, the sticky bits are indicated by the ☆ symbol. Also, all state machines that are not associated with sticky functionality are reset.
	When PERST is asserted low, the XIO2001 generates an internal PCI Express reset as defined in the PCI Express specification.
	When PERST transitions from low to high, a system power good condition is assumed by the XIO2001.	In addition, the XIO2001 asserts the internal PCI bus reset.
	Note: The system must assert PERST before power is removed, before REFCLK is removed or before REFCLK becomes unstable.	When the rising edge of PERST occurs, the XIO2001 samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The XIO2001 starts link training within 80 ms after PERST is deasserted.
PCI Express training control hot reset	The XIO2001 responds to a training control hot reset received on the PCI Express interface. After a training control hot reset, the PCI Express interface enters the DL_DOWN state.	In the DL_DOWN state, all remaining configuration register bits and state machines are reset. All remaining bits exclude sticky bits and EEPROM loadable bits. All remaining state machines exclude sticky functionality and EEPROM functionality.
		Within the configuration register maps, the sticky bits are indicated by the ☆ symbol and the EEPROM loadable bits are indicated by the † symbol.
		In addition, the XIO2001 asserts the internal PCI bus reset.
PCI bus reset PRST	System software has the ability to assert and deassert the PRST terminal on the secondary PCI bus interface. This terminal is the PCI bus reset.	When bit 6 (SRST) in the bridge control register at offset 3Eh (see Section 8.4.30) is asserted, the bridge asserts the PRST terminal. A 0 in the SRST bit deasserts the PRST terminal.