JAJSQ97 データシート

JAJSQ97J may 2009 – january 2021 XIO2001

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PNP|128
- MPQF060E
ZWS|169
- MPBGAK4B
ZAJ|144
- MPBG878A

サーマルパッド・メカニカル・データ

PNP|128
- PPTD154D

発注情報

6.8 PCI Express Differential Reference Clock Input Ranges⁽¹⁾

PARAMETER	TERMINALS	MIN	NOM	MAX	UNIT	COMMENTS
f_IN-DIFF Differential input frequency	REFCLK+ REFCLK–		100		MHz	The input frequency is 100 MHz + 300 ppm and –2800 ppm including SSC-dictated variations.
f_IN-SE Single-ended input frequency	REFCLK+		125		MHz	The input frequency is 125 MHz + 300 ppm and –300 ppm.
V_RX-DIFFp-p Differential input peak-to-peak voltage	REFCLK+ REFCLK–	0.175		1.2	V	V_RX-DIFFp-p = 2*\|V_REFCLK+ – V_REFCLK-\|
V_IH-SE	REFCLK+	0.7 V_{DDA_33}		V_{DDA_33}	V	Single-ended, reference clock mode high-level input voltage
V_IL-SE	REFCLK+	0		0.3 V_{DDA_33}	V	Single-ended, reference clock mode low-level input voltage
V_RX-CM-ACp AC peak common mode input voltage	REFCLK+ REFCLK–			140	mV	V_RX-CM-ACp = RMS(\|V_REFCLK+ + V_REFCLK-\|/2 V_RX-CM-DC) V_RX-CM-DC = DC_(avg) of \|V_REFCLK+ + V_REFCLK-\|/2
Duty cycle	REFCLK+ REFCLK–	40%		60%		Differential and single-ended waveform input duty cycle
Z_C-DC Clock source DC impedance	REFCLK+ REFCLK–	40		60	Ω	REFCLK± dc differential mode impedance
Z_RX-DC DC input impedance	REFCLK+ REFCLK–		20		kΩ	REFCLK+ dc single-ended mode impedance

(1) The XIO2001 is compliant with the defined system jitter models for a PCI-Express reference clock and associated TX/RX link. Any usage of the XIO2001 in a system configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter budgets.

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

サーマルパッド・メカニカル・データ

発注情報

6.8 PCI Express Differential Reference Clock Input Ranges(1)

6.8 PCI Express Differential Reference Clock Input Ranges⁽¹⁾