JAJSQ97J may   2009  – january 2021 XIO2001

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
    1.     Pin Assignments
    2.     Pin Descriptions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information #GUID-4E9F689A-942D-492C-8F28-F3CC5F1BD0E6/SCPS2129637AN1
    5. 6.5  Nominal Power Consumption
    6. 6.6  PCI Express Differential Transmitter Output Ranges
    7. 6.7  PCI Express Differential Receiver Input Ranges
    8. 6.8  PCI Express Differential Reference Clock Input Ranges #GUID-60875016-888B-4DD4-A309-543B497BAC9F/SCPS1718455
    9. 6.9  PCI Bus Electrical Characteristics
    10. 6.10 3.3-V I/O Electrical Characteristics
    11. 6.11 PCI Bus Timing Requirements
    12. 6.12 Power-Up/-Down Sequencing
      1. 6.12.1 Power-Up Sequence
      2. 6.12.2 Power-Down Sequence
  8. Parameter Measurement Information
    1.     25
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bridge Reset Features
      2. 8.3.2  PCI Express Interface
        1. 8.3.2.1 2.5-Gb/s Transmit and Receive Links
        2. 8.3.2.2 Transmitter Reference Resistor
        3. 8.3.2.3 Reference Clock
        4. 8.3.2.4 Reset
        5. 8.3.2.5 Beacon
        6. 8.3.2.6 Wake
        7. 8.3.2.7 Initial Flow Control Credits
        8. 8.3.2.8 PCI Express Message Transactions
      3. 8.3.3  PCI Port Arbitration
        1. 8.3.3.1 Classic PCI Arbiter
      4. 8.3.4  Configuration Register Translation
      5. 8.3.5  PCI Interrupt Conversion to PCI Express Messages
      6. 8.3.6  PME Conversion to PCI Express Messages
      7. 8.3.7  PCI Express to PCI Bus Lock Conversion
      8. 8.3.8  Two-Wire Serial-Bus Interface
        1. 8.3.8.1 Serial-Bus Interface Implementation
        2. 8.3.8.2 Serial-Bus Interface Protocol
        3. 8.3.8.3 Serial-Bus EEPROM Application
        4. 8.3.8.4 Accessing Serial-Bus Devices Through Software
      9. 8.3.9  Advanced Error Reporting Registers
      10. 8.3.10 Data Error Forwarding Capability
      11. 8.3.11 General-Purpose I/O Interface
      12. 8.3.12 Set Slot Power Limit Functionality
      13. 8.3.13 PCI Express and PCI Bus Power Management
      14. 8.3.14 Auto Pre-Fetch Agent
    4. 8.4 Register Maps
      1. 8.4.1  Classic PCI Configuration Space
      2. 8.4.2  Vendor ID Register
      3. 8.4.3  Device ID Register
      4. 8.4.4  Command Register
      5. 8.4.5  Status Register
      6. 8.4.6  Class Code and Revision ID Register
      7. 8.4.7  Cache Line Size Register
      8. 8.4.8  Primary Latency Timer Register
      9. 8.4.9  Header Type Register
      10. 8.4.10 BIST Register
      11. 8.4.11 Device Control Base Address Register
      12. 8.4.12 Primary Bus Number Register
      13. 8.4.13 Secondary Bus Number Register
      14. 8.4.14 Subordinate Bus Number Register
      15. 8.4.15 Secondary Latency Timer Register
      16. 8.4.16 I/O Base Register
      17. 8.4.17 I/O Limit Register
      18. 8.4.18 Secondary Status Register
      19. 8.4.19 Memory Base Register
      20. 8.4.20 Memory Limit Register
      21. 8.4.21 Prefetchable Memory Base Register
      22. 8.4.22 Prefetchable Memory Limit Register
      23. 8.4.23 Prefetchable Base Upper 32-Bit Register
      24. 8.4.24 Prefetchable Limit Upper 32-Bit Register
      25. 8.4.25 I/O Base Upper 16-Bit Register
      26. 8.4.26 I/O Limit Upper 16-Bit Register
      27. 8.4.27 Capabilities Pointer Register
      28. 8.4.28 Interrupt Line Register
      29. 8.4.29 Interrupt Pin Register
      30. 8.4.30 Bridge Control Register
      31. 8.4.31 Capability ID Register
      32. 8.4.32 Next Item Pointer Register
      33. 8.4.33 Subsystem Vendor ID Register
      34. 8.4.34 Subsystem ID Register
      35. 8.4.35 Capability ID Register
      36. 8.4.36 Next Item Pointer Register
      37. 8.4.37 Power Management Capabilities Register
      38. 8.4.38 Power Management Control/Status Register
      39. 8.4.39 Power Management Bridge Support Extension Register
      40. 8.4.40 Power Management Data Register
      41. 8.4.41 MSI Capability ID Register
      42. 8.4.42 Next Item Pointer Register
      43. 8.4.43 MSI Message Control Register
      44. 8.4.44 MSI Message Lower Address Register
      45. 8.4.45 MSI Message Upper Address Register
      46. 8.4.46 MSI Message Data Register
      47. 8.4.47 PCI Express Capability ID Register
      48. 8.4.48 Next Item Pointer Register
      49. 8.4.49 PCI Express Capabilities Register
      50. 8.4.50 Device Capabilities Register
      51. 8.4.51 Device Control Register
      52. 8.4.52 Device Status Register
      53. 8.4.53 Link Capabilities Register
      54. 8.4.54 Link Control Register
      55. 8.4.55 Link Status Register
      56. 8.4.56 Serial-Bus Data Register
      57. 8.4.57 Serial-Bus Word Address Register
      58. 8.4.58 Serial-Bus Slave Address Register
      59. 8.4.59 Serial-Bus Control and Status Register
      60. 8.4.60 GPIO Control Register
      61. 8.4.61 GPIO Data Register
      62. 8.4.62 TL Control and Diagnostic Register 0
      63. 8.4.63 Control and Diagnostic Register 1
      64. 8.4.64 Control and Diagnostic Register 2
      65. 8.4.65 Subsystem Access Register
      66. 8.4.66 General Control Register
      67. 8.4.67 Clock Control Register
      68. 8.4.68 Clock Mask Register
      69. 8.4.69 Clock Run Status Register
      70. 8.4.70 Arbiter Control Register
      71. 8.4.71 Arbiter Request Mask Register
      72. 8.4.72 Arbiter Time-Out Status Register
      73. 8.4.73 Serial IRQ Mode Control Register
      74. 8.4.74 Serial IRQ Edge Control Register
      75. 8.4.75 Serial IRQ Status Register
      76. 8.4.76 Pre-Fetch Agent Request Limits Register
      77. 8.4.77 Cache Timer Transfer Limit Register
      78. 8.4.78 Cache Timer Lower Limit Register
      79. 8.4.79 Cache Timer Upper Limit Register
    5. 8.5 PCI Express Extended Configuration Space
      1. 8.5.1  Advanced Error Reporting Capability ID Register
      2. 8.5.2  Next Capability Offset/Capability Version Register
      3. 8.5.3  Uncorrectable Error Status Register
      4. 8.5.4  Uncorrectable Error Mask Register
      5. 8.5.5  Uncorrectable Error Severity Register
      6. 8.5.6  Correctable Error Status Register
      7. 8.5.7  Correctable Error Mask Register
      8. 8.5.8  Advanced Error Capabilities and Control Register
      9. 8.5.9  Header Log Register
      10. 8.5.10 Secondary Uncorrectable Error Status Register
      11. 8.5.11 Secondary Uncorrectable Error Severity
      12. 8.5.12 Secondary Error Capabilities and Control Register
      13. 8.5.13 Secondary Header Log Register
    6. 8.6 Memory-Mapped TI Proprietary Register Space
      1. 8.6.1  Device Control Map ID Register
      2. 8.6.2  Revision ID Register
      3. 8.6.3  GPIO Control Register
      4. 8.6.4  GPIO Data Register
      5. 8.6.5  Serial-Bus Data Register
      6. 8.6.6  Serial-Bus Word Address Register
      7. 8.6.7  Serial-Bus Slave Address Register
      8. 8.6.8  Serial-Bus Control and Status Register
      9. 8.6.9  Serial IRQ Mode Control Register
      10. 8.6.10 Serial IRQ Edge Control Register
      11. 8.6.11 Serial IRQ Status Register
      12. 8.6.12 Pre-Fetch Agent Request Limits Register
      13. 8.6.13 Cache Timer Transfer Limit Register
      14. 8.6.14 Cache Timer Lower Limit Register
      15. 8.6.15 Cache Timer Upper Limit Register
  10. Application, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 In-Card Implementation
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 VCCP Clamping Rail
          2. 9.2.1.1.2 Combined Power Outputs
          3. 9.2.1.1.3 Auxiliary Power
          4. 9.2.1.1.4 VSS and VSSA Pins
          5. 9.2.1.1.5 Capacitor Selection Recommendations
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 PCI Bus Interface
            1. 9.2.1.2.1.1 Bus Parking
            2. 9.2.1.2.1.2 I/O Characteristics
            3. 9.2.1.2.1.3 Clamping Voltage
            4. 9.2.1.2.1.4 PCI Bus Clock Run
            5. 9.2.1.2.1.5 PCI Bus External Arbiter
            6. 9.2.1.2.1.6 MSI Messages Generated from the Serial IRQ Interface
            7. 9.2.1.2.1.7 PCI Bus Clocks
      2. 9.2.2 External EEPROM
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 JTAG Interface
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 Combined Power
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 Power Filtering
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 1.5-V and 3.3-V Digital Supplies
      2. 9.4.2 1.5-V and 3.3-V Analog Supplies
      3. 9.4.3 1.5-V PLL Supply
      4. 9.4.4 Power-Up/Down Sequencing
      5. 9.4.5 Power Supply Filtering Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documents Conventions
      1. 10.1.1 XIO2001 Definition
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documents
        1. 10.2.1.1 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報
PCI Bus Interface

The XIO2001 has a 32-bit PCI interface that can operate at 25 MHz, 33 MHz, 50 MHz or 66 MHz. This interface is compliant with the PCI Local Bus Specification , Revision 2.3 and 3.0. The remainder of this section describes implementation considerations for the XIO2001 secondary PCI bus interface.

  • AD31:0, C/ BE[3:0], PAR, DEVSEL, FRAME, STOP, TRDY, PERR, SERR, and IRDY are required signals and must be connected to each PCI bus device. The maximum signal loading specification for a 66 MHz bus is 30 pF and for a 33 MHz bus is 50 pF. PCI bus approved pullup resistors connected to VCCP are needed on the following terminals: IRDY, TRDY, FRAME, STOP, PERR, SERR, and DEVSEL.
  • The XIO2001 supports up to six external PCI bus devices with individual CLKOUT, REQ, and GNT signals. An internal PCI bus clock generator function provides six low-skew clock outputs. Plus, there are six REQ inputs and six GNT outputs from the internal PCI bus arbiter. Each PCI bus device connects to one CLKOUT signal, one REQ signal, and one GNT signal. All three signals are point-to- point connections. Unused CLKOUT signals can be disabled by asserting the appropriate CLOCK_DISABLE bit in the clock control register at offset D8h. Unused REQ signals can be disabled using a weak pullup resistor to VCCP. Unused GNT signals are no connects.
  • An external clock feedback feature is provided to de-skew PCI bus clocks. Connecting the CLKOUT[6] terminal to the CLK terminal is required if any of the other six CLKOUT[5:0] terminals are used to clock PCI bus devices. The CLKOUT signals should be slightly longer than the longest synchronous PCI bus signal trace. Figure 9-2 illustrates the external PCI bus clock feedback feature. The use of series resistors on the seven PCI bus clocks should be considered to reduce circuit board EMI.
    Note:

    There is one exception to this length matching rule associated with connecting a CLKOUT signal to PCI socket. For this case, the CLKOUT signal connected to a PCI socket should be 2.5 inches shorter than the other CLKOUT signals.

    GUID-2B49E960-EB2A-4775-B1FB-CDEEE0D62A83-low.gifFigure 9-2 External PCI Bus Clock Configuration
  • The XIO2001 has options providing for four different PCI clock frequencies: 25 MHz, 33 MHz, 50 MHz, and 66MHz. The clock frequency provided is determined by the states of the M66EN and PCLK66_SEL terminals at the de-assertion of PERST.
  • The PCLK66_SEL terminal determines if the XIO2001 provides either the standard 33/66 MHz frequencies or 25/50 MHz frequencies. If this terminal is pulled high at the de-assertion of PERST, then CLKOUTx terminals provide the standard PCI 33/66 MHz frequencies (depending on the state of M66EN). If the terminal is pulled low at the de-assertion of PERST, then a 25/50 MHz frequency is provided instead. The determination of what frequency to use is design-specific, and this terminal must be pulled high or low appropriately.
  • The M66EN terminal determines if the PCI Bus will operate at low speed (50/25 MHz) or high speed (66/33 MHz). At the de-assertion of PERST, the M66EN terminal is checked and if it is pulled to VCCP, then the high-speed (66 MHz or 50 MHz) frequencies are used. If the pin is low, then the low-speed (33 MHz or 25 MHz) frequencies are used. If the speed of all devices attached to the PCI bus is known, then this terminal can be pulled appropriately to set the speed of the PCI bus. If add-in card slots are present on a high-speed bus that may have low speed devices attached, then the terminal can be pulled high and connected to the slot, permitting the add-in card to pull the terminal low and reduce the bus speed if a low-speed card is inserted.
  • IDSEL for each PCI bus device must be resistively coupled (100 Ω) to one of the address lines between AD31 and AD16. Please refer to the XIO2001 Data Manual for the configuration register transaction device number to AD bit translation chart.
  • PCI interrupts can be routed to the INT[D:A] inputs on the XIO2001. These four inputs are asynchronous to the PCI bus clock and will detect state changes even if the PCI bus clock is stopped. For each INT[D:A] input, an approved PCI bus pullup resistor to VCCP is required to keep each interrupt signal from floating. Interrupts on the XIO2001 that are not connected to any device may be tied together and pulled-up through a single resistor.
  • PRST is a required PCI bus signal and must be connected to all devices. This output signal is asynchronous to the PCI bus clock. Since the output driver is always enabled and either driving high or low, no pullup resistor is needed.
  • LOCK is an optional PCI bus signal. If LOCK is present in a system, it is connected to each PCI bus device that supports the feature and must meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to VCCP is required to keep this signal from floating, even if it is not connected to devices on the bus. LOCK is a bused signal and synchronous to the PCI bus clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.
  • SERIRQ is an optional PCI bus signal. When PERST is de-asserted, if a pullup resistor to VCCP is detected on terminal M08, the serial IRQ interface is enabled. A pulldown resistor to V SS disables this feature. If SERIRQ is present in a system, it is connected to each PCI bus device that supports the feature and must meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to VCCP is required to keep this signal from floating. SERIRQ is a bused signal and synchronous to the PCI bus clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.
    Note:

    SERIRQ does not support serialized PCI interrupts and is used for serializing the 16 ISA interrupts.

  • CLKRUN is an optional PCI bus signal that is shared with the GPIO0 pin. When PERST is de-asserted and if a pullup resistor to VDD_33 is detected on pin C11 (CLKRUN_EN), the clock run feature is enabled. If CLKRUN is required in a system, this pin is connected to each PCI bus device and must meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to VDD_33 is required per the PCI Mobile Design Guide . CLKRUN is a bused signal and synchronous to the PCI bus clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.
    Note:

    If CLKRUN is used in a system, it must be supported by all devices attached to the PCI bus; if a device that does not support CLKRUN is attached to a bus where it is enabled, there is a danger that it will not be able to have a clock when it requires one.

  • PWR_OVRD is an optional PCI bus signal that is shared with the GPIO1 terminal. In PWR_OVRD mode, this pin is always an output and is asynchronous to the PCI bus clock. When the power override control bits in the general control register at offset D4h are set to 001b or 011b, the M09 pin operates as the PWR_OVRD signal. Prior to setting the power override control bits, the GPIO1 // PWR_OVRD pin defaults to a standard GPIO pin.
  • PME is an optional PCI bus input terminal to detect power management events from downstream devices. The PME terminal is operational during both main power states and VAUX states. The PME receiver has hysteresis and expects an asynchronous input signal. The board design requirements associated with this PME terminal are the same whether or not the terminal is connected to a downstream device. If the system includes a VAUX supply, the PME terminal requires a weak pullup resistor connected to VAUX to keep the terminal from floating. If no VAUX supply is present, the pullup resistor is connected to VDD_33.
  • The bridge supports external PCI bus clock sources. If an external clock is a system requirement, the external clock source is connected to the CLK terminal. The trace length relationship between the synchronous bus signals and the external clock signals that is previously described is still required to meet PCI bus setup and hold. For external clock mode, all seven CLKOUT[6:0] terminals can be disabled using the clock control register at offset D8h. Plus, the XIO2001 clock run feature must be disabled with external PCI bus clocks because there is no method of turning off external clocks.
    Note:

    If an external clock with a frequency higher than 33 MHz is used, the M66EN terminal must be pulled up for the XIO2001 to function correctly.

  • The XIO2001 supports an external PCI bus arbiter. When PERST is deasserted, the logic state of the EXT_ARB_EN pin is checked. If an external arbiter is required, EXT_ARB_EN is connected to VDD_33. When connecting the XIO2001 to an external arbiter, the external arbiter’s REQ signal is connected to the XIO2001 0 GNT output terminal. Likewise, the GNT signal from the external arbiter is connected to the XIO2001 0 REQ input pin. Unused REQ signals on the XIO2001 should be tied together and connected to VCCP through a pull-up resistor. When in external arbiter mode, all internal XIO2001 port arbitration features are disabled. Figure 9-3 illustrates the connectivity of an external arbiter.
    GUID-DD2F4DB1-F0DF-408A-8FBC-016E40258997-low.gifFigure 9-3 External Arbiter Connections