The XIO2001 has a 32-bit PCI interface that can operate at 25 MHz, 33 MHz, 50 MHz or 66 MHz. This interface is compliant with the PCI Local Bus Specification , Revision 2.3 and 3.0. The remainder of this section describes implementation considerations for the XIO2001 secondary PCI bus interface.

• AD31:0, C/ BE[3:0], PAR, DEVSEL, FRAME, STOP, TRDY, PERR, SERR, and IRDY are required signals and must be connected to each PCI bus device. The maximum signal loading specification for a 66 MHz bus is 30 pF and for a 33 MHz bus is 50 pF. PCI bus approved pullup resistors connected to V_CCP are needed on the following terminals: IRDY, TRDY, FRAME, STOP, PERR, SERR, and DEVSEL.
• The XIO2001 supports up to six external PCI bus devices with individual CLKOUT, REQ, and GNT signals. An internal PCI bus clock generator function provides six low-skew clock outputs. Plus, there are six REQ inputs and six GNT outputs from the internal PCI bus arbiter. Each PCI bus device connects to one CLKOUT signal, one REQ signal, and one GNT signal. All three signals are point-to- point connections. Unused CLKOUT signals can be disabled by asserting the appropriate CLOCK_DISABLE bit in the clock control register at offset D8h. Unused REQ signals can be disabled using a weak pullup resistor to V_CCP. Unused GNT signals are no connects.
• An external clock feedback feature is provided to de-skew PCI bus clocks. Connecting the CLKOUT[6] terminal to the CLK terminal is required if any of the other six CLKOUT[5:0] terminals are used to clock PCI bus devices. The CLKOUT signals should be slightly longer than the longest synchronous PCI bus signal trace. Figure 9-2 illustrates the external PCI bus clock feedback feature. The use of series resistors on the seven PCI bus clocks should be considered to reduce circuit board EMI.
  Note:

  There is one exception to this length matching rule associated with connecting a CLKOUT signal to PCI socket. For this case, the CLKOUT signal connected to a PCI socket should be 2.5 inches shorter than the other CLKOUT signals.

  Figure 9-2 External PCI Bus Clock Configuration
• The XIO2001 has options providing for four different PCI clock frequencies: 25 MHz, 33 MHz, 50 MHz, and 66MHz. The clock frequency provided is determined by the states of the M66EN and PCLK66_SEL terminals at the de-assertion of PERST.
• The PCLK66_SEL terminal determines if the XIO2001 provides either the standard 33/66 MHz frequencies or 25/50 MHz frequencies. If this terminal is pulled high at the de-assertion of PERST, then CLKOUTx terminals provide the standard PCI 33/66 MHz frequencies (depending on the state of M66EN). If the terminal is pulled low at the de-assertion of PERST, then a 25/50 MHz frequency is provided instead. The determination of what frequency to use is design-specific, and this terminal must be pulled high or low appropriately.
• The M66EN terminal determines if the PCI Bus will operate at low speed (50/25 MHz) or high speed (66/33 MHz). At the de-assertion of PERST, the M66EN terminal is checked and if it is pulled to V_CCP, then the high-speed (66 MHz or 50 MHz) frequencies are used. If the pin is low, then the low-speed (33 MHz or 25 MHz) frequencies are used. If the speed of all devices attached to the PCI bus is known, then this terminal can be pulled appropriately to set the speed of the PCI bus. If add-in card slots are present on a high-speed bus that may have low speed devices attached, then the terminal can be pulled high and connected to the slot, permitting the add-in card to pull the terminal low and reduce the bus speed if a low-speed card is inserted.
• IDSEL for each PCI bus device must be resistively coupled (100 Ω) to one of the address lines between AD31 and AD16. Please refer to the XIO2001 Data Manual for the configuration register transaction device number to AD bit translation chart.
• PCI interrupts can be routed to the INT[D:A] inputs on the XIO2001. These four inputs are asynchronous to the PCI bus clock and will detect state changes even if the PCI bus clock is stopped. For each INT[D:A] input, an approved PCI bus pullup resistor to V_CCP is required to keep each interrupt signal from floating. Interrupts on the XIO2001 that are not connected to any device may be tied together and pulled-up through a single resistor.
• PRST is a required PCI bus signal and must be connected to all devices. This output signal is asynchronous to the PCI bus clock. Since the output driver is always enabled and either driving high or low, no pullup resistor is needed.
• LOCK is an optional PCI bus signal. If LOCK is present in a system, it is connected to each PCI bus device that supports the feature and must meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to V_CCP is required to keep this signal from floating, even if it is not connected to devices on the bus. LOCK is a bused signal and synchronous to the PCI bus clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.
• SERIRQ is an optional PCI bus signal. When PERST is de-asserted, if a pullup resistor to V_CCP is detected on terminal M08, the serial IRQ interface is enabled. A pulldown resistor to V SS disables this feature. If SERIRQ is present in a system, it is connected to each PCI bus device that supports the feature and must meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to V_CCP is required to keep this signal from floating. SERIRQ is a bused signal and synchronous to the PCI bus clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.
  Note:

  SERIRQ does not support serialized PCI interrupts and is used for serializing the 16 ISA interrupts.

• CLKRUN is an optional PCI bus signal that is shared with the GPIO0 pin. When PERST is de-asserted and if a pullup resistor to V_{DD_33} is detected on pin C11 (CLKRUN_EN), the clock run feature is enabled. If CLKRUN is required in a system, this pin is connected to each PCI bus device and must meet PCI bus loading requirements for the selected clock frequency. An approved PCI bus pullup resistor to V_{DD_33} is required per the PCI Mobile Design Guide . CLKRUN is a bused signal and synchronous to the PCI bus clock. All synchronous PCI bus signals must be length matched to meet clock setup and hold requirements.
  Note:

  If CLKRUN is used in a system, it must be supported by all devices attached to the PCI bus; if a device that does not support CLKRUN is attached to a bus where it is enabled, there is a danger that it will not be able to have a clock when it requires one.

• PWR_OVRD is an optional PCI bus signal that is shared with the GPIO1 terminal. In PWR_OVRD mode, this pin is always an output and is asynchronous to the PCI bus clock. When the power override control bits in the general control register at offset D4h are set to 001b or 011b, the M09 pin operates as the PWR_OVRD signal. Prior to setting the power override control bits, the GPIO1 // PWR_OVRD pin defaults to a standard GPIO pin.
• PME is an optional PCI bus input terminal to detect power management events from downstream devices. The PME terminal is operational during both main power states and V_AUX states. The PME receiver has hysteresis and expects an asynchronous input signal. The board design requirements associated with this PME terminal are the same whether or not the terminal is connected to a downstream device. If the system includes a V_AUX supply, the PME terminal requires a weak pullup resistor connected to V_AUX to keep the terminal from floating. If no V_AUX supply is present, the pullup resistor is connected to V_{DD_33}.
• The bridge supports external PCI bus clock sources. If an external clock is a system requirement, the external clock source is connected to the CLK terminal. The trace length relationship between the synchronous bus signals and the external clock signals that is previously described is still required to meet PCI bus setup and hold. For external clock mode, all seven CLKOUT[6:0] terminals can be disabled using the clock control register at offset D8h. Plus, the XIO2001 clock run feature must be disabled with external PCI bus clocks because there is no method of turning off external clocks.
  Note:

  If an external clock with a frequency higher than 33 MHz is used, the M66EN terminal must be pulled up for the XIO2001 to function correctly.

• The XIO2001 supports an external PCI bus arbiter. When PERST is deasserted, the logic state of the EXT_ARB_EN pin is checked. If an external arbiter is required, EXT_ARB_EN is connected to V_{DD_33}. When connecting the XIO2001 to an external arbiter, the external arbiter’s REQ signal is connected to the XIO2001 0 GNT output terminal. Likewise, the GNT signal from the external arbiter is connected to the XIO2001 0 REQ input pin. Unused REQ signals on the XIO2001 should be tied together and connected to V_CCP through a pull-up resistor. When in external arbiter mode, all internal XIO2001 port arbitration features are disabled. Figure 9-3 illustrates the connectivity of an external arbiter.
  Figure 9-3 External Arbiter Connections