JAJSQ97 データシート

JAJSQ97J may 2009 – january 2021 XIO2001

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PNP|128
- MPQF060E
ZWS|169
- MPBGAK4B
ZAJ|144
- MPBG878A

サーマルパッド・メカニカル・データ

PNP|128
- PPTD154D

発注情報

8.4.1 Classic PCI Configuration Space

The programming model of the XIO2001 PCI-Express to PCI bridge is compliant to the classic PCI-to-PCI bridge programming model. The PCI configuration map uses the type 1 PCI bridge header.

All bits marked with a are sticky bits and are reset by a global reset ( GRST) or the internally-generated power-on reset. All bits marked with a ☆ are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset, PERST, GRST, or the internally-generated power-on reset.

Table 8-11 Classic PCI Configuration Register Map

REGISTER NAME				OFFSET
Device ID		Vendor ID		000h
Status		Command		004h
Class code			Revision ID	008h
BIST	Header type	Latency timer	Cache line size	00Ch
Device control base address				010h
Reserved				014h
Secondary latency timer	Subordinate bus number	Secondary bus number	Primary bus number	018h
Secondary status		I/O limit	I/O base	01Ch
Memory limit		Memory base		020h
Prefetchable memory limit		Prefetchable memory base		024h
Prefetchable base upper 32 bits				028h
Prefetchable limit upper 32 bits				02Ch
I/O limit upper 16 bits		I/O base upper 16 bits		030h
Reserved			Capabilities pointer	034h
Expansion ROM base address				038h
Bridge control		Interrupt pin	Interrupt line	03Ch
Reserved		Next item pointer	SSID/SSVID CAP ID	040h
Subsystem ID⁽¹⁾		Subsystem vendor ID⁽¹⁾		044h
Power management capabilities		Next item pointer	PM CAP ID	048h
PM Data	PMCSR_BSE	Power management CSR		04Ch
MSI message control		Next item pointer	MSI CAP ID	050h
MSI message address				054h
MSI upper message address				058h
Reserved		MSI message data		05Ch
MSI Mask Bits Register				060h
MSI Pending Bits Register				064h
Reserved				068h–06Ch
PCI Express capabilities register		Next item pointer	PCI Express capability ID	070h
Device Capabilities				074h
Device status		Device control		078h
Link Capabilities				07Ch
Link status		Link control		080h
Slot Capabilities				084h
Slot Status		Slot Control		088h
Root Capabilities		Root Control		08Ch
Root Status				090h
Device Capabilities 2				094h
Device Status 2		Device Control 2		098h
Link Capabilities 2				09Ch
Link Status 2		Link Control 2		0A0h
Slot Capabilities 2				0A4h
Slot Status 2		Slot Control 2		0A8h
Reserved				0ACh
Serial-bus control and status⁽¹⁾	Serial-bus slave address⁽¹⁾	Serial-bus word address⁽¹⁾	Serial-bus data⁽¹⁾	0B0h
GPIO data⁽¹⁾		GPIO control⁽¹⁾		0B4h
Reserved				0B8h–0BCh
TL Control and diagnostic register 0⁽¹⁾				0C0h
DLL Control and diagnostic register 1⁽¹⁾				0C4h
PHY Control and diagnostic register 2⁽¹⁾				0C8h
Reserved				0CCh
Subsystem access⁽¹⁾				0D0h
General control⁽¹⁾				0D4h
Reserved	Clock run status⁽¹⁾	Clock mask	Clock control	0D8h
Reserved	Arbiter time-out status	Arbiter request mask⁽¹⁾	Arbiter control⁽¹⁾	0DCh
Serial IRQ edge control⁽¹⁾		Reserved	Serial IRQ mode control⁽¹⁾	0E0h
Reserved		Serial IRQ status		0E4h
Cache Timer Transfer Limit		PFA Request Limit		0E8h
Cache Timer Upper Limit		Cache Timer Lower Limit		0ECh
Reserved				0F0h–0FCh

(1) One or more bits in this register are reset by a PCI Express reset ( PERST), a GRST, or the internally-generated power-on reset. Registers highlighted in gray are reserved or not implemented.