JAJSQ97 データシート | TI.com

JAJSQ97J may 2009 – january 2021 XIO2001

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

PNP|128
- MPQF060E
ZWS|169
- MPBGAK4B
ZAJ|144
- MPBG878A

サーマルパッド・メカニカル・データ

PNP|128
- PPTD154D

発注情報

6.11 PCI Bus Timing Requirements

over recommended operating conditions⁽¹⁾

PARAMETER		TEST CONDITION	33 MHz		66 MHz		UNIT
PARAMETER		TEST CONDITION	MIN	MAX	MIN	MAX	UNIT
t_pd	CLK to shared signal valid propagation delay time	C_L = 50 pF		11			ns
	CLK to shared signal valid propagation delay time	C_L = 30 pF				6
	CLK to shared signal invalid propagation delay time	C_L = 50 pF	2
	CLK to shared signal invalid propagation delay time	C_L = 30 pF			1
t_ON	tEnable time, high-impedance-to-active delay time from CLK	C_L = 50 pF	2				ns
t_ON	tEnable time, high-impedance-to-active delay time from CLK	C_L = 30 pF			1		ns
t_OFF	Disable time, active-to-high-impedance delay time from CLK	C_L = 50 pF		28			ns
t_OFF	Disable time, active-to-high-impedance delay time from CLK	C_L = 30 pF				14	ns
t_su	Setup time on shared signals before CLK valid (rising edge)		7		3		ns
t_h	Hold time on shared signals after CLK valid (rising edge)		0		0		ns

(1) The PCI shared signals are AD31:0, C/BE[3:0], FRAME, TRDY, IRDY, STOP, IDSEL, DEVSEL, LOCK, SERIRQ, PAR, PERR, SERR, and CLKRUN.