JAJSQ97J may   2009  – january 2021 XIO2001

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Revision History
  6. Pin Configuration and Functions
    1.     Pin Assignments
    2.     Pin Descriptions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information #GUID-4E9F689A-942D-492C-8F28-F3CC5F1BD0E6/SCPS2129637AN1
    5. 6.5  Nominal Power Consumption
    6. 6.6  PCI Express Differential Transmitter Output Ranges
    7. 6.7  PCI Express Differential Receiver Input Ranges
    8. 6.8  PCI Express Differential Reference Clock Input Ranges #GUID-60875016-888B-4DD4-A309-543B497BAC9F/SCPS1718455
    9. 6.9  PCI Bus Electrical Characteristics
    10. 6.10 3.3-V I/O Electrical Characteristics
    11. 6.11 PCI Bus Timing Requirements
    12. 6.12 Power-Up/-Down Sequencing
      1. 6.12.1 Power-Up Sequence
      2. 6.12.2 Power-Down Sequence
  8. Parameter Measurement Information
    1.     25
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Bridge Reset Features
      2. 8.3.2  PCI Express Interface
        1. 8.3.2.1 2.5-Gb/s Transmit and Receive Links
        2. 8.3.2.2 Transmitter Reference Resistor
        3. 8.3.2.3 Reference Clock
        4. 8.3.2.4 Reset
        5. 8.3.2.5 Beacon
        6. 8.3.2.6 Wake
        7. 8.3.2.7 Initial Flow Control Credits
        8. 8.3.2.8 PCI Express Message Transactions
      3. 8.3.3  PCI Port Arbitration
        1. 8.3.3.1 Classic PCI Arbiter
      4. 8.3.4  Configuration Register Translation
      5. 8.3.5  PCI Interrupt Conversion to PCI Express Messages
      6. 8.3.6  PME Conversion to PCI Express Messages
      7. 8.3.7  PCI Express to PCI Bus Lock Conversion
      8. 8.3.8  Two-Wire Serial-Bus Interface
        1. 8.3.8.1 Serial-Bus Interface Implementation
        2. 8.3.8.2 Serial-Bus Interface Protocol
        3. 8.3.8.3 Serial-Bus EEPROM Application
        4. 8.3.8.4 Accessing Serial-Bus Devices Through Software
      9. 8.3.9  Advanced Error Reporting Registers
      10. 8.3.10 Data Error Forwarding Capability
      11. 8.3.11 General-Purpose I/O Interface
      12. 8.3.12 Set Slot Power Limit Functionality
      13. 8.3.13 PCI Express and PCI Bus Power Management
      14. 8.3.14 Auto Pre-Fetch Agent
    4. 8.4 Register Maps
      1. 8.4.1  Classic PCI Configuration Space
      2. 8.4.2  Vendor ID Register
      3. 8.4.3  Device ID Register
      4. 8.4.4  Command Register
      5. 8.4.5  Status Register
      6. 8.4.6  Class Code and Revision ID Register
      7. 8.4.7  Cache Line Size Register
      8. 8.4.8  Primary Latency Timer Register
      9. 8.4.9  Header Type Register
      10. 8.4.10 BIST Register
      11. 8.4.11 Device Control Base Address Register
      12. 8.4.12 Primary Bus Number Register
      13. 8.4.13 Secondary Bus Number Register
      14. 8.4.14 Subordinate Bus Number Register
      15. 8.4.15 Secondary Latency Timer Register
      16. 8.4.16 I/O Base Register
      17. 8.4.17 I/O Limit Register
      18. 8.4.18 Secondary Status Register
      19. 8.4.19 Memory Base Register
      20. 8.4.20 Memory Limit Register
      21. 8.4.21 Prefetchable Memory Base Register
      22. 8.4.22 Prefetchable Memory Limit Register
      23. 8.4.23 Prefetchable Base Upper 32-Bit Register
      24. 8.4.24 Prefetchable Limit Upper 32-Bit Register
      25. 8.4.25 I/O Base Upper 16-Bit Register
      26. 8.4.26 I/O Limit Upper 16-Bit Register
      27. 8.4.27 Capabilities Pointer Register
      28. 8.4.28 Interrupt Line Register
      29. 8.4.29 Interrupt Pin Register
      30. 8.4.30 Bridge Control Register
      31. 8.4.31 Capability ID Register
      32. 8.4.32 Next Item Pointer Register
      33. 8.4.33 Subsystem Vendor ID Register
      34. 8.4.34 Subsystem ID Register
      35. 8.4.35 Capability ID Register
      36. 8.4.36 Next Item Pointer Register
      37. 8.4.37 Power Management Capabilities Register
      38. 8.4.38 Power Management Control/Status Register
      39. 8.4.39 Power Management Bridge Support Extension Register
      40. 8.4.40 Power Management Data Register
      41. 8.4.41 MSI Capability ID Register
      42. 8.4.42 Next Item Pointer Register
      43. 8.4.43 MSI Message Control Register
      44. 8.4.44 MSI Message Lower Address Register
      45. 8.4.45 MSI Message Upper Address Register
      46. 8.4.46 MSI Message Data Register
      47. 8.4.47 PCI Express Capability ID Register
      48. 8.4.48 Next Item Pointer Register
      49. 8.4.49 PCI Express Capabilities Register
      50. 8.4.50 Device Capabilities Register
      51. 8.4.51 Device Control Register
      52. 8.4.52 Device Status Register
      53. 8.4.53 Link Capabilities Register
      54. 8.4.54 Link Control Register
      55. 8.4.55 Link Status Register
      56. 8.4.56 Serial-Bus Data Register
      57. 8.4.57 Serial-Bus Word Address Register
      58. 8.4.58 Serial-Bus Slave Address Register
      59. 8.4.59 Serial-Bus Control and Status Register
      60. 8.4.60 GPIO Control Register
      61. 8.4.61 GPIO Data Register
      62. 8.4.62 TL Control and Diagnostic Register 0
      63. 8.4.63 Control and Diagnostic Register 1
      64. 8.4.64 Control and Diagnostic Register 2
      65. 8.4.65 Subsystem Access Register
      66. 8.4.66 General Control Register
      67. 8.4.67 Clock Control Register
      68. 8.4.68 Clock Mask Register
      69. 8.4.69 Clock Run Status Register
      70. 8.4.70 Arbiter Control Register
      71. 8.4.71 Arbiter Request Mask Register
      72. 8.4.72 Arbiter Time-Out Status Register
      73. 8.4.73 Serial IRQ Mode Control Register
      74. 8.4.74 Serial IRQ Edge Control Register
      75. 8.4.75 Serial IRQ Status Register
      76. 8.4.76 Pre-Fetch Agent Request Limits Register
      77. 8.4.77 Cache Timer Transfer Limit Register
      78. 8.4.78 Cache Timer Lower Limit Register
      79. 8.4.79 Cache Timer Upper Limit Register
    5. 8.5 PCI Express Extended Configuration Space
      1. 8.5.1  Advanced Error Reporting Capability ID Register
      2. 8.5.2  Next Capability Offset/Capability Version Register
      3. 8.5.3  Uncorrectable Error Status Register
      4. 8.5.4  Uncorrectable Error Mask Register
      5. 8.5.5  Uncorrectable Error Severity Register
      6. 8.5.6  Correctable Error Status Register
      7. 8.5.7  Correctable Error Mask Register
      8. 8.5.8  Advanced Error Capabilities and Control Register
      9. 8.5.9  Header Log Register
      10. 8.5.10 Secondary Uncorrectable Error Status Register
      11. 8.5.11 Secondary Uncorrectable Error Severity
      12. 8.5.12 Secondary Error Capabilities and Control Register
      13. 8.5.13 Secondary Header Log Register
    6. 8.6 Memory-Mapped TI Proprietary Register Space
      1. 8.6.1  Device Control Map ID Register
      2. 8.6.2  Revision ID Register
      3. 8.6.3  GPIO Control Register
      4. 8.6.4  GPIO Data Register
      5. 8.6.5  Serial-Bus Data Register
      6. 8.6.6  Serial-Bus Word Address Register
      7. 8.6.7  Serial-Bus Slave Address Register
      8. 8.6.8  Serial-Bus Control and Status Register
      9. 8.6.9  Serial IRQ Mode Control Register
      10. 8.6.10 Serial IRQ Edge Control Register
      11. 8.6.11 Serial IRQ Status Register
      12. 8.6.12 Pre-Fetch Agent Request Limits Register
      13. 8.6.13 Cache Timer Transfer Limit Register
      14. 8.6.14 Cache Timer Lower Limit Register
      15. 8.6.15 Cache Timer Upper Limit Register
  10. Application, Implementation, and Layout
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 In-Card Implementation
        1. 9.2.1.1 Design Requirements
          1. 9.2.1.1.1 VCCP Clamping Rail
          2. 9.2.1.1.2 Combined Power Outputs
          3. 9.2.1.1.3 Auxiliary Power
          4. 9.2.1.1.4 VSS and VSSA Pins
          5. 9.2.1.1.5 Capacitor Selection Recommendations
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 PCI Bus Interface
            1. 9.2.1.2.1.1 Bus Parking
            2. 9.2.1.2.1.2 I/O Characteristics
            3. 9.2.1.2.1.3 Clamping Voltage
            4. 9.2.1.2.1.4 PCI Bus Clock Run
            5. 9.2.1.2.1.5 PCI Bus External Arbiter
            6. 9.2.1.2.1.6 MSI Messages Generated from the Serial IRQ Interface
            7. 9.2.1.2.1.7 PCI Bus Clocks
      2. 9.2.2 External EEPROM
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 JTAG Interface
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
      4. 9.2.4 Combined Power
        1. 9.2.4.1 Design Requirements
        2. 9.2.4.2 Detailed Design Procedure
      5. 9.2.5 Power Filtering
        1. 9.2.5.1 Design Requirements
        2. 9.2.5.2 Detailed Design Procedure
    3. 9.3 Layout
      1. 9.3.1 Layout Guidelines
      2. 9.3.2 Layout Example
    4. 9.4 Power Supply Recommendations
      1. 9.4.1 1.5-V and 3.3-V Digital Supplies
      2. 9.4.2 1.5-V and 3.3-V Analog Supplies
      3. 9.4.3 1.5-V PLL Supply
      4. 9.4.4 Power-Up/Down Sequencing
      5. 9.4.5 Power Supply Filtering Recommendations
  11. 10Device and Documentation Support
    1. 10.1 Documents Conventions
      1. 10.1.1 XIO2001 Definition
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documents
        1. 10.2.1.1 ドキュメントの更新通知を受け取る方法
    3. 10.3 サポート・リソース
    4. 10.4 Trademarks
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Pin Descriptions

The following list describes the different input/output cell types that appear in the pin function tables:

  • HS DIFF IN = High speed differential input
  • HS DIFF OUT = High speed differential output
  • PCI BUS = PCI bus tri-state bidirectional buffer with 3.3-V or 5.0-V clamp rail.
  • LV CMOS = 3.3-V low voltage CMOS input or output with 3.3-V clamp rail
  • BIAS = Input/output terminals that generate a bias voltage to determine a driver's operating current
  • Feed through = These terminals connect directly to macros within the part and not through an input or output cell.
  • PWR = Power terminal
  • GND = Ground terminal
Pin Functions
SIGNAL ZWS
BALL NO.
ZAJ
BALL NO.
PNP
PIN NO.
I/O TYPE EXTERNAL PARTS DESCRIPTION
POWER SUPPLY
PCIR A01, K03 D03, J03 2, 27 I/O Resistor PCI Rail. 5.0-V or 3.3-V PCI bus clamp voltage to set maximum I/O voltage tolerance of the secondary PCI bus signals. Connect each one of these terminals to the secondary PCI bus I/O clamp rail through a 1kΩ resistor.
VDD_15 G04, K07, D07, H10, G10 J08, H08, J07, G08, K13, G11 21, 53, 113 PWR Bypass capacitors 1.5-V digital core power terminals
VDD_15_PLL F10 F11 84 PWR Pi filter 1.5-V power terminal for internal PLL. This terminal must be isolated from analog and digital power.
VDDA_15 F13, H13 E12, H12 76, 78, 83, 85 PWR Pi filter 1.5-V analog power terminal
VDD_33 E04, H03, J04, L08, K09, D09, C07, D05, J12 E05, G06, H07, G07, H06, F08, F07, F06, J11 7, 19, 33, 46, 62, 100, 111, 126 PWR Bypass capacitors 3.3-V digital I/O power terminal
VDD_33_AUX J11 J12 73 PWR Bypass capacitors 3.3-V auxiliary power terminal Note: This terminal is connected to VSS through a pulldown resistor if no auxiliary supply is present.
VDDA_33 D13 C12 74, 92 PWR Pi filter 3.3-V analog power terminal
GROUND
VSS D04, F04, H04, K04, K05, K06, K08, L11, J10, D10, D08, D06, F11, F12 E06, F05, G05, H05, J05, J06, J09, H09, E09, E08, E07, F12 ,F09 GND Digital ground terminals
VSS E05, E06, E07, E08, E09, F05, F06, F07, F08, F09, G05, G06, G07, G08, G09, H05, H06, H07, H08, H09, J05, J06, J07, J08, J09 GND Ground terminals for thermally-enhanced package
VSSA K10, C11, H12, G11, E11, E10 G09, B12, J13, G12, F13, D12 79, 82, 86, 89 GND Analog ground terminal
COMBINED POWER OUTPUT
VDD_15_COMB L13 N13 69 Feed
through
Bypass capacitors Internally-combined 1.5-V main and VAUX power output for external bypass capacitor filtering. Supplies all internal 1.5-V circuitry powered by VAUX.

Caution: Do not use this terminal to supply external power to other devices.

VDD_33_COMB J13 K12 75 Feed
through
Bypass capacitors Internally-combined 3.3-V main and VAUX power output for external bypass capacitor filtering. Supplies all internal 3.3-V circuitry powered by VAUX.

Caution: Do not use this terminal to supply external power to other devices.

VDD_33_COMBIO K11 K11 70 Feed
through
Bypass capacitors Internally-combined 3.3-V main and VAUX power output for external bypass capacitor filtering. Supplies all internal 3.3-V input/output circuitry powered by VAUX.

Caution: Do not use this terminal to supply external power to other devices.

Pin Functions
SIGNAL ZWS
BALL NO.
ZAJ
BALL NO.
PNP
PIN NO.
I/O
TYPE
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
DESCRIPTION
PCI EXPRESS
CLKREQ D11 D11 91 0 LV CMOS VDD_33_ COMBIO Clock request. When asserted low, requests upstream device start clock in cases where clock may be removed in L1.

Note: Since CLKREQ is an open-drain output buffer, a system side pullup resistor is required.

PERST H11 H11 77 I LV CMOS VDD_33_ COMBIO PCI Express reset input. The PERST signal identifies when the system power is stable and generates an internal power on reset.

Note: The PERST input buffer has hysteresis.

REFCLK125_SEL B13 A13 95 I LV CMOS VDD_33 Pullup or pulldown resistor Reference clock select. This terminal selects the reference clock input.

0 = 100-MHz differential common reference clock used.

1 = 125-MHz single-ended, reference clock used.

REFCLK+ C13 C13 93 DI HS DIFF IN VDD_33 Reference clock. REFCLK+ and REFCLK– comprise the differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, use the REFCLK+ input.
REFCLK– C12 B13 94 DI HS DIFF IN VDD_33 Capacitor for VSS for single-ended node Reference clock. REFCLK+ and REFCLK– comprise the differential input pair for the 100-MHz system reference clock. For a single-ended, 125-MHz system reference clock, attach a capacitor from REFCLK– to VSS.
REF0_PCIE
REF1_PCIE
K12
K13
M13
L13
71
72
I/O BIAS External resistor External reference resistor + and – terminals for setting TX driver current. An external resistance of 14,532-Ω is connected between REF0_PCIE and REF1_PCIE terminals. To eliminate the need for a custom resistor, two series resistors are recommended: a 14.3-kΩ, 1% resistor and a 232-Ω, 1% resistor.
RXP
RXN
E13
E12
E13
D13
87
88
DI HS DIFF IN VSS High-speed receive pair. RXP and RXN comprise the differential receive pair for the single PCI Express lane supported.
TXP
TXN
G13
G12
H13
G13
80
81
DO HS DIFF OUT VDD_15 Series capacitor High-speed transmit pair. TXP and TXN comprise the differential transmit pair for the single PCI Express lane supported.
WAKE M13 L12 68 O LV CMOS VDD_33_ COMBIO Wake is an active low signal that is driven low to reactivate the PCI Express link hierarchy’s main power rails and reference clocks.

Note: Since WAKE is an open-drain output buffer, a system side pullup resistor is required.

PCI SYSTEM
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
N05
N04
L05
M05
N03
M04
N02
M03
L04
M02
L03
M01
L02
L01
K02
K01
E01
E02
E03
D01
D02
C01
C02
D03
C03
B02
C04
A02
B03
B04
A03
C05
N05
L05
M05
N04
N03
L04
M04
N02
L03
M02
N01
L02
K02
M01
K03
L01
F02
E03
E01
E02
D01
C01
D02
B01
A01
B03
C03
A02
A03
C04
C05
B04
44
43
42
41
40
39
38
37
35
34
32
31
30
29
28
26
12
11
10
9
8
6
5
4
1
128
127
125
124
123
122
121
I/O PCI Bus PCIR PCI address data lines
C/BE[3]
C/BE[2]
C/BE[1]
C/BE[0]
N01
J03
F02
B01
M03
K01
F03
C02
36
25
14
3
I/O PCI Bus PCIR PCI command byte enables
CLK F03 F01 13 I PCI Bus PCIR PCI clock input. This is the clock input to the PCI bus core.
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUT6
B05
B06
A07
B07
A09
A10
B11
B05
B06
B07
A07
A08
A10
C10
120
117
114
112
107
104
99
O PCI Bus PCIR PCI clock outputs. These clock outputs are used to clock the PCI bus. If the bridge PCI bus clock outputs are used, then CLKOUT6 must be connected to the CLK input.
DEVSEL H02 H02 20 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI device select
FRAME J02 J01 24 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI frame
GNT5
GNT4
GNT3
GNT2
GNT1
GNT0
B10
A11
B09
B08
C06
A05
B11
B10
B09
B08
A06
A05
101
103
106
109
115
118
O PCI Bus PCIR PCI grant outputs. These signals are used for arbitration when the PCI bus is the secondary bus and an external arbiter is not used. GNT0 is used as the REQ for the bridge when an external arbiter is used.
INTA
INTB
INTC
INTD
M06
N06
M07
L07
N06
L06
M07
N07
47
48
49
50
I PCI Bus PCIR Pullup resistor per PCI spec PCI interrupts A–D. These signals are interrupt inputs to the bridge on the secondary PCI bus.
IRDY J01 H03 23 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI initiator ready
LOCK M08 N08 54 I/O PCI Bus PCIR Pullup resistor per PCI spec This terminal functions as PCI LOCK

Note: In lock mode, an external pullup resistor is required to prevent the LOCK signal from floating.

M66EN L06 M06 45 I PCI Bus PCIR Pullup resistor per PCI spec 66-MHz mode enable

0 = Secondary PCI bus and clock outputs operate at 33 MHz. If PCLK66_SEL is low then the frequency will be 25 MHz.

1 = Secondary PCI bus and clock outputs operate at 66 MHz. If PCLK66_SEL is low then the frequency will be 50 MHz.

PAR F01 G01 15 I/O PCI Bus PCIR PCI bus parity
PERR G02 G03 17 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI parity error
PME L12 M12 67 I LV CMOS VDD_33_ COMBIO Pullup resistor per PCI spec Pullup resistor per PCI spec PCI power management event. This terminal may be used to detect PME events from a PCI device on the secondary bus.

Note: The PME input buffer has hysteresis.

REQ5
REQ4
REQ3
REQ2
REQ1
REQ0
A12
C09
C08
A08
A06
A04
C09
A09
C08
C07
C06
A04
102
105
108
110
116
119
I PCI Bus PCIR If unused, a weak pullup resistor per PCI spec PCI request inputs. These signals are used for arbitration on the secondary PCI bus when an external arbiter is not used. REQ0 is used as the GNT for the bridge when an external arbiter is used.
PRST N07 L07 51 O PCI Bus PCIR PCI reset. This terminal is an output to the secondary PCI bus.
SERR G03 G02 16 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI system error
STOP G01 H01 18 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI stop
TRDY H01 J02 22 I/O PCI Bus PCIR Pullup resistor per PCI spec PCI target ready
JTAG
JTAG_TCK M12 N12 65 I LV CMOS VDD_33 Optional pullup resistor JTAG test clock input. This signal provides the clock for the internal TAP controller.

Note: This terminal has an internal active pullup resistor. The pullup is active at all times.

Note: This terminal should be tied to ground or pulled low if JTAG is not required.

JTAG_TDI N12 L10 63 I LV CMOS VDD_33 Optional pullup resistor JTAG test data input. Serial test instructions and data are received on this terminal.

Note: This terminal has an internal active pullup resistor. The pullup is active at all times.

Note: This terminal can be left unconnected if JTAG is not required.

JTAG_TDO M11 N11 61 O LV CMOS VDD_33 JTAG test data output. This terminal the serial output for test instructions and data.

Note: This terminal can be left unconnected if JTAG is not required.

JTAG_TMS L10 L11 64 I LV CMOS VDD_33 Optional pullup resistor JTAG test mode select. The signal received at JTAG_TMS is decoded by the internal TAP controller to control test operations.

Note: This terminal has an internal active pullup resistor. The pullup is active at all times.

Note: This terminal can be left unconnected if JTAG is not required.

JTAG_TRST L09 L09 60 I LV CMOS VDD_33 Optional pullup resistor JTAG test reset. This terminal provides Optional for asynchronous initialization of the TAP controller.

Note: This terminal has an internal active pullup resistor. The pullup is active at all times.

Note: This terminal should be tied to ground or pulled low if JTAG is not required.

Miscellaneous Pins
SIGNAL ZWS
BALL NO.
ZAJ
BALL NO.
PNP
PIN NO.
I/O
TYPE
CELL
TYPE
CLAMP
RAIL
EXTERNAL
PARTS
DESCRIPTION
CLKRUN_
EN
A13 C11 96 I LV CMOS VDD_33 Optional pullup/
pulldown
resistor
Clock run enable

0 = Clock run support disabled

1 = Clock run support enabled

EXT_ARB_EN C10 A12 97 I LV CMOS VDD_33 Optional pullup/
pulldown
resistor

External arbiter enable

0 = Internal arbiter enabled

1 = External arbiter enabled

GPIO0 //
CLKRUN
N09 N09 55 I/O LV CMOS VDD_33 Optional pullup resistor

General-purpose I/O 0/clock run. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see Section 8.4.60) or the clock run terminal. This terminal is used as clock run input when the bridge is placed in clock run mode.

Note: In clock run mode, an external pullup resistor is required to prevent the CLKRUN signal from floating.

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

GPIO1 // PWR_
OVRD
M09 M09 56 I/O LV CMOS VDD_33

General-purpose I/O 1/power override. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in the GPIO control register (see Section 8.4.60) or the power override output terminal. GPIO1 becomes PWR_OVRD when bits 22:20 (POWER_OVRD) in the general control register are set to 001b or 011b (see Section 8.4.66).

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

GPIO2 N10 N10 57 I/O LV CMOS VDD_33

General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (see Section 8.4.60).

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

GPIO3 // SDA N11 L08 58 I/O LV CMOS VDD_33 Optional pullup resistor

GPIO3 or serial-bus data. This terminal functions as serial-bus data if a pullup resistor is detected on SCL or when the SBDETECT bit is set in the Serial Bus Control and Status Register (see Section 8.4.59). If no pullup is detected then this terminal functions as GPIO3.

Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA signal from floating.

GPIO4 // SCL M10 M10 59 I/O LV CMOS VDD_33 Optional pullup resistor

GPIO4 or serial-bus clock. This terminal functions as serial-bus clock if a pullup resistor is detected on SCL or when the SBDETECT bit is set in the Serial Bus Control and Status Register (see Section 8.4.59). If no pullup is detected then this terminal functions as GPIO4.

Note: In serial-bus mode, an external pullup resistor is required to prevent the SCL signal from floating.

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

GRST N13 M11 66 I LV CMOS VDD_33
_COMBIO

Global reset input. Asynchronously resets all logic in device, including sticky bits and power management state machines.

Note: The GRST input buffer has both hysteresis and an internal active pullup. The pullup is active at all times.

PCLK66_
SEL
B12 A11 98 I LV CMOS VDD_33 Optional pulldown resistor

PCI clock select. This terminal determines the default PCI clock frequency driven out the CLKOUTx terminals.

0 = 50 MHz PCI Clock

1 = 66 MHz PCI Clock

Note: This terminal has an internal active pullup resistor. This pullup is active at all times.

Note: M66EN terminal also has an affect of PCI clock frequency.

SERIRQ N08 M08 52 I/O PCI Bus PCIR Pullup or pulldown resistor

Serial IRQ interface. This terminal functions as a serial IRQ interface if a pullup is detected when PERST is deasserted. If a pulldown is detected, then the serial IRQ interface is disabled.

VREG_
PD33
D12 E11 90 I LV CMOS VDD_33
_COMBIO
Pulldown resistor 3.3-V voltage regulator powerdown. This terminal should always be tied directly to ground or an optional pulldown resistor can be used.