JAJS366D October   2006  – October 2024 XTR111

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configurations and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Explanation of Pin Functions
      2. 6.3.2 Dynamic Performance
      3. 6.3.3 External Current Limit
      4. 6.3.4 External MOSFET
      5. 6.3.5 Output Error Flag and Disable Input
      6. 6.3.6 Voltage Regulator
      7. 6.3.7 Level Shift of 0V Input and Transconductance Trim
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input Voltage
      2. 7.1.2 Error Flag Delay
      3. 7.1.3 Voltage Output Configuration
      4. 7.1.4 4mA-to-20mA Output
    2. 7.2 Typical Applications
      1. 7.2.1 0mA–20mA Voltage-to-Current Converter
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Additional Applications
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package and Heat Dissipation
        2. 7.4.1.2 Thermal Pad Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 サード・パーティ製品に関する免責事項
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

at TA = 25°C, VVSP = 24V, RSET = 2.0kΩ, REGF connected to REGS; OD = low, and external FET connected (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TRANSMITTER
Transfer function IOUT = 10 × VVIN / RSET
IOUT Specified output current Specified performance(1) 0.1 25 mA
Derated performance(2) 0 to 32 mA
Current limit for output current 41 ±9 mA
Nonlinearity, IOUT/ISET(2)(3) IOUT = 0.1mA to 25mA 0.002 0.02 % of Span
IOUT = 0.1mA to 32mA 0.004 % of Span
IOS Offset current IOUT = 4mA(1) 0.002 0.02 % of Span
TA = –40°C to +85°C 0.0002 0.001 % of Span/°C
8V to 40V supply 0.0001 0.005 % of Span/V
Span Error, IOUT/ISET(2) IOUT = 0.1mA to 25mA 0.015 0.1 % of Span
TA = –40°C to +85°C (1)(2) 5 ppm/°C
8V to 40V supply(1) 0.0001 % of Span/V
Output resistance From drain of QEXT(4) > 1 GΩ
Output leakage OD = high < 1 μA
Input impedance (VIN) 2.4 || 30 GΩ || pF
IB Input bias current (VIN) 15 25 nA
VOS Input offset voltage(2) VVIN = 20mV 0.3 1.5 mV
TA = –40°C to +85°C 1.5 μV/°C
VVIN Input voltage(5) TA = –40°C to +85°C 0 to 12 V
Noise, referred to input(2) f = 0.1Hz to 10Hz, IOUT = 4mA 2.5 μVPP
Dynamic response See Section 6.3.2
V-REGULATOR OUTPUT (REGF)
Voltage reference(6) RLOAD = 5kΩ 2.85 3.0 3.15 V
TA = –40°C to +85°C(6) 30 ppm/°C
8V to 40V supply(6) 0.1 mV/V
Bias current into REGS(6) 0.8 μA
Load regulation IREGF = 0.6mA to 5mA 3 5 mV/mA
Supply regulation(6) RLOAD = 5kΩ 0.01 mV/V
Output current 5 mA
Short-circuit output current 21 mA
DIGITAL INPUT (OD)
VIL Low-level threshold TA = –40°C to +85°C 0.6 V
VIH High-level threshold TA = –40°C to +85°C 1.8 V
Internal pullup current VOD < 5.5V 4 μA
DIGITAL OUTPUT (EF)
IOH Leakage current (open drain) 1 μA
VOL Low-level output voltage IEF = 2.2mA 0.8 V
IOL Low-level output current VEF = 400mV 2 mA
POWER SUPPLY
IQ Quiescent current(6) IOUT = 0mA 450 550 μA
(1) Includes input amplifier, but excludes RSET tolerance. Offset current is the deviation from the current ratio of ISET to IIS (output current).
(2) See also Section 5.6.
(3) Span is the change in output current resulting from a full-scale change in input voltage.
(4) Within compliance range limited by (+VVSP – 2V) + VDS required for linear operation of QEXT.
(5) See also Section 7.1.1.
(6) See also Section 5.6.