The ADS1257 is a low-noise, 30-kSPS, 24-bit, delta-sigma (ΔΣ) analog-to-digital converter (ADC) with an integrated multiplexer (mux), input buffer, and programmable gain amplifier (PGA) in a small 20-pin, 5-mm × 5-mm VQFN package. The combination of integration, high conversion rate, and 24-bit resolution together in a small package makes the device ideally suited for space-constrained applications.
The input multiplexer accepts either two differential or three single-ended input measurements. The sensor-break detection circuit verifies the input connection continuity to the ADC. The selectable input buffer greatly increases the input impedance, and in many cases, eliminates the need for external buffers. The buffer input voltage range includes AGND. The low-noise PGA provides gains from 1 to 64 to accommodate a wide range of inputs signals. The programmable digital filter optimizes ADC resolution (up to 23 bits noise-free) and conversion rates (up to 30 kSPS). The digital filter provides single-cycle settled conversions, and rejection of 50-Hz and 60-Hz interference signals.
The SPI-compatible serial interface operates with as little as three wires, simplifying connections to external controllers. Integrated calibration features support both self and system correction of offset and gain errors for all PGA gain settings. Two bidirectional digital I/Os pins control external circuits.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADS1257 | VQFN (20) | 5.00 mm × 5.00 mm |
Changes from A Revision (October 2015) to B Revision
Changes from * Revision (September 2015) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | REFP | Analog input | Positive reference input |
2 | AIN0 | Analog input | Analog input 0; Leave unconnected or connect to AVDD if not used(4) |
3 | AIN1 | Analog input | Analog input 1; Leave unconnected or connect to AVDD if not used(4) |
4 | AIN2 | Analog input | Analog input 2; Leave unconnected or connect to AVDD if not used(4) |
5 | AIN3 | Analog input | Analog input 3; Leave unconnected or connect to AVDD if not used(4) |
6 | SYNC/PWDN | Digital input(1)(2) | Synchronization or power-down input, active low; Connect to DVDD if not used(4) |
7 | RESET | Digital input(1)(2) | Reset input, active low; Connect to DVDD if not used(4) |
8 | DVDD | Digital | Digital power supply; Connect decoupling capacitor to DGND |
9 | DGND | Digital | Digital ground |
10 | CLKIN | Digital input(2) | External clock input |
11 | CS | Digital input(1)(2) | Chip select, active low; Connect to DGND if not used |
12 | DRDY | Digital output | Data ready output; active low |
13 | DOUT | Digital output | Serial data output |
14 | DIN | Digital input(1)(2) | Serial data input |
15 | SCLK | Digital input(1)(2) | Serial clock input |
16 | D0/CLKOUT | Digital input/output(3) | General-purpose digital I/O 0 or clock output(4) |
17 | D1 | Digital input/output(3) | General-purpose digital I/O 1(4) |
18 | AVDD | Analog | Analog power supply; Connect decoupling capacitor to AGND |
19 | AGND | Analog | Analog ground |
20 | REFN | Analog input | Negative reference input |
Thermal Pad | — | Thermal power pad; Connect to AGND |