DLPU078A july 2019 – may 2023 DLP230NP , DLPC3436
Table 3-63 describes the write parameters.
MSB | Byte 1 | LSB | |||||
---|---|---|---|---|---|---|---|
b7 | b6 | b5 | b4 | b3 | b2 | b1 | b0 |
Bit | Type | Description |
---|---|---|
7:3 | R |
Reserved |
2:0 | W | Input source format
|
When adjusting the XPR FPGA Video Format selection, the parallel video data input must be properly aligned with the 24-bit bus of the FPGA. The appropriate data encoding format is provided in Figure 3-3.