DLPU100B May   2020  – June 2024 DLP2021-Q1 , DLP3021-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
    1. 1.1 Purpose and Scope
  5. 2FPGA Pin Configuration and Functions
    1. 2.1 DMD Interface
    2. 2.2 Light Control
    3. 2.3 Communication
    4. 2.4 Support
    5. 2.5 FPGA Dedicated Pins
    6. 2.6 Power and Ground
    7. 2.7 Unused Pins
  6. 3Specifications
    1. 3.1 Recommended Operating Conditions
    2. 3.2 FPGA Power Consumption
    3. 3.3 Host SPI Interface Timing
    4. 3.4 Power Supply and Reset Timing
      1. 3.4.1 Power-Up Timing
      2. 3.4.2 Power-Down Timing
      3. 3.4.3 Brownout Detection
    5. 3.5 DMD Interface Timing
    6. 3.6 Flash Memory Interface Timing
    7. 3.7 Reference Clock Timing
    8. 3.8 I2C Interface Timing
  7. 4Feature Descriptions
    1. 4.1 Video Control
      1. 4.1.1 Video Options
      2. 4.1.2 Example 1: Display a Static Image
      3. 4.1.3 Example 2: Display 1 Video Repeatedly
      4. 4.1.4 Example 3: Display Two Videos Then Stop
      5. 4.1.5 Example 4: Display a Video Once and Then Display an Image Forever
      6. 4.1.6 Example 5: Display 3+ Videos/Images Seamlessly
    2. 4.2 Temperature Measurements
    3. 4.3 PWM Outputs
    4. 4.4 Host IRQ Interrupt Signal
    5. 4.5 Video and Image Compression
  8. 5Layout
  9. 6Host Command Protocol
    1. 6.1 SPI Specifications
    2. 6.2 SPI Write Command
    3. 6.3 SPI Read Command
  10. 7FPGA Register Definitions
  11. 8Revision History

2.5 FPGA Dedicated Pins

The following pins are hardware-dedicated on Spartan 7 FPGA. For primary guidelines, see Xilinx documentation. Descriptions in Table 2-5 are recommendations for application-specific consideration.

Table 2-5 FPGA Dedicated Pin Descriptions
PIN I/O DESCRIPTION
NAME NUMBER
PUDC B10 I Pullup during configuration

Tie either directly (or through a 1-KΩ or less resistor) to GND. This will enable pullups on pins during configuration.
PROGRAMZ N8 I Asynchronous reset to configuration logic (active low)
INITZ N7 B (open drain) Indicates initialization of configuration memory (active low)
DONE M9 B Indicates successful completion of configuration (active high)
CFGBVS_0 N9 I Tie to ground
DXN_0 J7 N/A Temperature-sensing diode pin for FPGA. Tie to ground if not used.
DXP_0 J8 N/A Temperature-sensing diode pin for FPGA. Tie to ground if not used.
M0_0 L10 I Configuration mode select

Tie to 1.8V.
M1_0 L8 I Configuration mode select

Tie to ground.
M2_0 L9 I Configuration mode select

Tie to ground.
HSTL VREF C4, L3 REF Voltage reference for HSTL 1.8-V input
TDO(1) M6 I JTAG data output
TDI(1) M7 I JTAG data input
TCK(1) A8 O JTAG clock
TMS(1) L7 I JTAG mode select
(1) This pin is not applicable to the DLP2021-Q1.