DLPU100B May 2020 – June 2024 DLP2021-Q1 , DLP3021-Q1
PARAMETER | VALUE |
---|---|
Clock Frequency | 5 MHz |
Mode (Clock Phase and Polarity) | 0 (Data captured on rising edge, transitions on falling edge. Clock idle low.) |
Bit order | Most significant bit first within a byte |
Byte order | Least significant byte first |
Chip select polarity | Active low |