DLPU132A October   2023  – March 2024 DLPC964

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 DLPLCRC964EVM Power Supply Requirements
      1. 2.1.1 External Power Supply Requirements
    2. 2.2 DLPLCRC964EVM Connections
      1. 2.2.1  J1, J2 - HPC FMC Connector (Male)
      2. 2.2.2  J3 - Input Power
      3. 2.2.3  J4 - TestMux Connector
      4. 2.2.4  J6, J8 - I2C Address Selectors
      5. 2.2.5  J7 - JTAG Boundary Scan
      6. 2.2.6  J9 - Micro-B USB Connector
      7. 2.2.7  J10 - I2C Connector
      8. 2.2.8  J11 - 3.3V GPIO Connector
      9. 2.2.9  J12 - 1.8V GPIO Connector
      10. 2.2.10 J13, J14, J15, J16 - DMD EVM Board Flex Cable Connectors
      11. 2.2.11 J17 - DMD_DMux Connector
      12. 2.2.12 J18 - FanSink Connector
      13. 2.2.13 Switches
        1. 2.2.13.1 SW1 - DMD park (PARK_Z)
        2. 2.2.13.2 SW2 - DLPC964 Reset
      14. 2.2.14 DLP LightCrafter DLPC964 LEDs
        1. 2.2.14.1 DLPLCRC964EVM Power and Status LEDs
    3. 2.3 EVM Assembly
      1. 2.3.1 DLPLCRC964EVM and DMD EVM Assembly
      2. 2.3.2 Connecting an Apps FPGA Board to the DLPLCRC964EVM
    4. 2.4 Quick Start
      1. 2.4.1 Power-up of the DLPLCRC964EVM
      2. 2.4.2 Power-down of the DLPLCRC964EVM
  9. 3Software
    1. 3.1 Operating the DLPLCRC964EVM
      1. 3.1.1 DLPLCRC964EVM GUI and Apps FPGA Software
      2. 3.1.2 PC Software
      3. 3.1.3 Menu Bar
      4. 3.1.4 Main Window
        1. 3.1.4.1 Start Page
        2. 3.1.4.2 DLPC964 Tab
          1. 3.1.4.2.1 DLPC964 Status
          2. 3.1.4.2.2 DLPC964 Reset
          3. 3.1.4.2.3 HSS Reset
          4. 3.1.4.2.4 I2C 7-bit Addr
          5. 3.1.4.2.5 Pattern Settings
        3. 3.1.4.3 DLPC964 Registers Tab
        4. 3.1.4.4 Apps FPGA Tab
          1. 3.1.4.4.1 Apps FPGA Status
          2. 3.1.4.4.2 Apps FPGA Reset
          3. 3.1.4.4.3 HSS Reset (Apps)
          4. 3.1.4.4.4 Apps I2C 7-bit Addr
          5. 3.1.4.4.5 Pattern Settings (Apps)
        5. 3.1.4.5 Apps FPGA Registers Tab
      5. 3.1.5 Programming Firmware
        1. 3.1.5.1 Connecting to the DLPC964 GUI
        2. 3.1.5.2 Programming the DLPC964 Controller
        3. 3.1.5.3 Programming the Apps FPGA (AMD EVM)
          1. 3.1.5.3.1 Programming the Apps FPGA with Bitstream Loading
          2. 3.1.5.3.2 Programming Apps FPGA by Flash
  10. 4Hardware Design Files
    1. 4.1 Schematics
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1. 5.1 Abbreviations and Acronyms
    2. 5.2 Trademarks
    3. 5.3 References
    4. 5.4 Safety
      1. 5.4.1 Caution Labels
  12. 6Related Documentation from Texas Instruments
  13. 7Revision History
3.1.4.2.5 Pattern Settings
GUID-20240223-SS0I-BWB2-QNFG-RTN2CPTHCWPQ-low.png Figure 3-10 DLPC964 Pattern Settings
  • Pattern Generator - When enabled, patterns are displayed onto the DMD. When disabled, no patterns are going to be displayed on DMD.
  • Pattern Cycle - When enabled, the DMD cycles through the first eight predefined patterns, each being displayed every 2 seconds. When disabled, a single selected pattern is sent to the DMD.
  • North/South Flip - Having this enabled flips the image being displayed on the DMD vertically.
  • Pattern Select
    • Full-On - Full white background where all mirrors on the DMD are going to be in the on position.
    • Full-Off - Full black background where all mirrors on the DMD are going to be in the off position.
    • Checkerboard - Black and white checkerboard (64 x 64 pixels).
    • Single pixel grid - The border is on to help visualize the extent of the DMD array.
    • W to E diagonal lines - Used to check for row data issues.
    • E to W diagonal lines - Used to check for row data issues.
    • Horizontal lines - Used to check for issues with row loads.
    • Vertical lines - Used to check for issues with data bus lines.
    • Load2 Checkboard - A black and white checkerboard pattern (32 x 32 pixels).
    • Dots 10 by 10 - Single white pixels are spaced 10 pixels evenly in the X and Y direction.
    • Inverting Checkerboard - Inverted version of the checkerboard pattern.
    • Random Noise - Randomized noise pattern for customer tilt angle testing.
    • 1x1 Horizontal lines (every row alternating black/white) - used to check for issues with row loads.
    • 1x1 Vertical lines (every column alternating black/white) - used to check for issues with data bus lines.
    • Full-On/Off - Toggles between the Full-On and Full-Off pattern.
  • Micromirror Reset Mode
    • Global Reset - In global reset mode, all enabled blocks are going to be loaded with data sequentially. Once all blocks have been loaded, the MCP_Start signal resets all the blocks at the same time.
    • Single Block Phased Reset - In single reset mode, a single block is loaded at a time and once the DLPC964 has loaded the DMD with the data sent, the MCP_Start signal resets that single block.
    • Block Clear with Global Reset - This mode shows how the Clear block load type is used in the DLPC964 system. A clear load type does not require any data since the block puts all of the mirrors in the off state (0). Since the clear load type does not have any data to be sent after, the command valid signal is not needed so only the DMD load signal is sent. The MCP_Start signal follows the same pattern as Global Mode.
    • Block Set with Global Reset - This mode shows how the Set block load type is used in the DLPC964 system. A set load type does the opposite of the clear load type and also does not require any data. The set load type sets all the mirrors in the on state (1). Just like the clear load type, there is no need for the command valid signal, only the DMD load signal. The MCP_Start signal follows the same pattern as Global Mode.
    • Single Block Phased Reset Slow Mode - Slow mode (or disabling the fast mode) causes the DLPC964 to receive data across a single channel only (4x 10Gbps lanes compared to 12x). To do this, each segment of a block must be sent sequentially across 1 Aurora 64B/66B channel instead of parallel. The segments must be sent in the following order: D (0x3) C (0x2) B (0x1) A (0x0). Once all four segments are sent, the MCP_Start signal can be issued. The MCP_Start signal behaves the same as in Single Mode.
  • Block Active - There are 16 blocks [0-15] in the DLP991U DMD. The blocks that are checked inside the GUI are going to determine what blocks are going to be reset and loaded with new data from the DMD.