JAJS124Q December   1999  – October 2019 UCC1895 , UCC2895 , UCC3895

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  ADS (Adaptive Delay Set)
      2. 7.3.2  CS (Current Sense)
      3. 7.3.3  CT (Oscillator Timing Capacitor)
      4. 7.3.4  DELAB and DELCD (Delay Programming Between Complementary Outputs)
      5. 7.3.5  EAOUT, EAP, and EAN (Error Amplifier)
      6. 7.3.6  OUTA, OUTB, OUTC, and OUTD (Output MOSFET Drivers)
      7. 7.3.7  PGND (Power Ground)
      8. 7.3.8  RAMP (Inverting Input of the PWM Comparator)
      9. 7.3.9  REF (Voltage Reference)
      10. 7.3.10 RT (Oscillator Timing Resistor)
      11. 7.3.11 GND (Analog Ground)
      12. 7.3.12 SS/DISB (Soft Start/Disable)
      13. 7.3.13 SYNC (Oscillator Synchronization)
      14. 7.3.14 VDD (Chip Supply)
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Programming DELAB, DELCD and the Adaptive Delay Set
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Power Loss Budget
        2. 8.2.2.2  Preliminary Transformer Calculations (T1)
        3. 8.2.2.3  QA, QB, QC, QD FET Selection
        4. 8.2.2.4  Selecting LS
        5. 8.2.2.5  Selecting Diodes DB and DC
        6. 8.2.2.6  Output Inductor Selection (LOUT)
        7. 8.2.2.7  Output Capacitance (COUT)
        8. 8.2.2.8  Select Rectifier Diodes
        9. 8.2.2.9  Input Capacitance (CIN)
        10. 8.2.2.10 Current Sense Network (CT, RCS, RR, DA)
          1. 8.2.2.10.1 Output Voltage Setpoint
          2. 8.2.2.10.2 Voltage Loop Compensation
          3. 8.2.2.10.3 Setting the Switching Frequency
          4. 8.2.2.10.4 Soft Start
          5. 8.2.2.10.5 Setting the Switching Delays
          6. 8.2.2.10.6 Setting the Slope Compensation
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
      2. 11.1.2 関連リンク
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 コミュニティ・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 Glossary
  12. 12メカニカル、パッケージ、および注文情報

8.2.2.9 Input Capacitance (CIN)

The input voltage in this design is 390 VDC, which is generally fed by the output of a PFC boost pre-regulator. The input capacitance is generally selected based on holdup and ripple requirements.

NOTE

The delay time needed to achieve ZVS can act as a duty cycle clamp (DCLAMP).

Calculate tank frequency:

Equation 72. UCC1895 UCC2895 UCC3895 qu74_lua560.gif

Estimated delay time:

Equation 73. UCC1895 UCC2895 UCC3895 qu75_lua560.gif

Effective duty cycle clamp (DCLAMP):

Equation 74. UCC1895 UCC2895 UCC3895 qu99_lusa16.gif

VDROP is the minimum input voltage where the converter can still maintain output regulation. The converter’s input voltage would only drop down this low during a brownout or line-drop condition if this converter was following a PFC pre-regulator.

Equation 75. UCC1895 UCC2895 UCC3895 eq_77_slus157.gif

CIN was calculated based on one line cycle of holdup:

Equation 76. UCC1895 UCC2895 UCC3895 qu78_lua560.gif

Calculate high frequency input capacitor RMS current (ICINRMS).

Equation 77. UCC1895 UCC2895 UCC3895 qu79_lua560.gif

To meet the input capacitance and RMS current requirements for this design a 330-µF capacitor was chosen from Panasonic part number EETHC2W331EA.

Equation 78. UCC1895 UCC2895 UCC3895 qu80_lua560.gif

This capacitor has a high frequency (ESRCIN) of 150 mΩ, measured with an impedance analyzer at 200 kHz.

Equation 79. UCC1895 UCC2895 UCC3895 qu81_lua560.gif

Estimate CIN power dissipation (PCIN):

Equation 80. UCC1895 UCC2895 UCC3895 qu82_lua560.gif

Recalculate remaining power budget:

Equation 81. UCC1895 UCC2895 UCC3895 eq_81_slus157.gif

There is roughly 5.0 W left in the power budget left for the current sensing network, and biasing the control device and all resistors supporting the control device.