JAJS177F November 2003 – February 2020 TPS2490 , TPS2491
PRODUCTION DATA.
In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the TPS2490 is set to a very low power limit setting, it has to regulate the FET current and hence the voltage across the sense resistor (VSNS) to a very low value. VSNS can be computed as shown in Equation 12:
To avoid significant degradation of the power limiting accuracy, a VSNS of less than 5 mV is not recommended. Based on this requirement the minimum allowed power limit can be computed as follows:
Because the VPROG pin, which programs the power limit of the device, has a minimum voltage of 0.4 V, the set PLIM must also result in the voltage at VPROG being greater than 0.4 V. Based on this requirement the minimum allowed power limit can be computed as follows:
Because the power limit has to satisfy both the VSNS and VPROG, the greater PLIM,MIN value is used as the basis for sizing the resistive divider. In this design example it is 50 W. The maximum ratio of the resistive divider can be computed as follows:
In Equation 16 R3 is picked as 41.2 kΩ. R3 must be greater than 4 kΩ, but TI recommends that 10 kΩ or greater be used. The resistive divider ratio is used to calculate R4, and next largest available resistor is chosen.
We choose 4.64 kΩ for our final value of R4.