JAJS194E January   2007  – June 2019 TPS40077

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      アプリケーション概略図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Pulse Duration
      2. 7.3.2  Slew Rate Limit On VDD
      3. 7.3.3  Setting The Switching Frequency (Programming The Clock Oscillator)
      4. 7.3.4  Loop Compensation
      5. 7.3.5  Shutdown and Sequencing
      6. 7.3.6  Boost and LVBP Bypass Capacitance
      7. 7.3.7  Internal Regulators
      8. 7.3.8  Power Dissipation
      9. 7.3.9  Boost Diode
      10. 7.3.10 Synchronous Rectifier Control
    4. 7.4 Programming
      1. 7.4.1 Programming The Ramp Generator Circuit and UVLO
      2. 7.4.2 Programming Soft Start
      3. 7.4.3 Programming Short-Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Regulator 8-V to 16-V Input, 1.8-V Output at 10 A
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Power Train Components
            1. 8.2.1.2.1.1  Output Inductor, LOUT
            2. 8.2.1.2.1.2  Output Capacitor, COUT, ELCO and MLCC
            3. 8.2.1.2.1.3  Input Capacitor, CIN ELCO and MLCC
            4. 8.2.1.2.1.4  Switching MOSFET, QSW
            5. 8.2.1.2.1.5  Rectifier MOSFET, QSR
            6. 8.2.1.2.1.6  Timing Resistor, RT
            7. 8.2.1.2.1.7  Feed-Forward and UVLO Resistor, RKFF
            8. 8.2.1.2.1.8  Soft-Start Capacitor, CSS
            9. 8.2.1.2.1.9  Short-Circuit Protection, RILIM and CILIM
            10. 8.2.1.2.1.10 Boost Voltage, CBOOST and DBOOST (Optional)
            11. 8.2.1.2.1.11 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
        3. 8.2.1.3 Application Curves
    3. 8.3 Additional System Examples
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10デバイスおよびドキュメントのサポート
    1. 10.1 デバイス・サポート
      1. 10.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 10.2 ドキュメントのサポート
      1. 10.2.1 関連資料
    3. 10.3 ドキュメントの更新通知を受け取る方法
    4. 10.4 コミュニティ・リソース
    5. 10.5 商標
    6. 10.6 静電気放電に関する注意事項
    7. 10.7 Glossary
  11. 11メカニカル、パッケージ、および注文情報

8.2.1.2.1.4 Switching MOSFET, QSW

The following key parameters must be met by the selected MOSFET.

  • Drain source voltage, Vds, must be able to withstand the input voltage plus spikes that may be on the switching node. For this design a Vds rating of 30 volts is recommended.
  • Drain current, ID, at 25°C, must be greater than that calculated using Equation 25.
    • Equation 25. TPS40077 q08_iqsw_lus714.gif
  • With the parameters specified, the calculation of IQSW(RMS) should be greater than 5 A.
  • Gate source voltage, Vgs, must be able to withstand the gate voltage from the control IC. For the TPS40077, this is 11 V.

Once the above boundary parameters are defined, the next step in selecting the switching MOSFET is to select the key performance parameters. Efficiency is the performance characteristic which drives the other selection criteria. Target efficiency for this design is 90%. Based on 1.8-V output and 10 A, this equates to a power loss in the converter of 1.8 W. Based on this figure, a target of 0.6 W dissipated in the switching FET was chosen.

Equation 26 through Equation 29 can be used to calculate the power loss, PQSW, in the switching MOSFET.

Equation 26. TPS40077 q09_pqsw_lus714.gif
Equation 27. TPS40077 q10_pcon_lus714.gif
Equation 28. TPS40077 q11_psw_lus714.gif
Equation 29. TPS40077 q12_pgate_lus714.gif

where

PCON = conduction losses

PSW = switching losses

PGATE = gate-drive losses

Qgd = drain-source charge or Miller charge

Qgs1 = gate-source post-threshold charge

Ig = gate-drive current

QOSS(SW) = switching MOSFET output charge

QOSS(SR) = synchronous MOSFET output charge

Qg(TOT) = total gate charge from zero volts to the gate voltage

Vg = gate voltage

If the total estimated loss is split evenly between conduction and switching losses, Equation 27 and Equation 28 yield preliminary values for RDS(on) and (Qgs1 + Qgd). Note output losses due to QOSS and gate losses have been ignored here. Once a MOSFET is selected, these parameters can be added.

The switching MOSFET for this design should have an RDS(on) of less than 8 mΩ. The sum of Qgd and Qgs should be approximately 4 nC.

It may not always be possible to get a MOSFET which meets both these criteria, so a compromise may be necessary. Also, by selecting different MOSFETs close to these criteria and calculating power loss, the final selection can be made. It was found that the Si7860DP MOSFET from Vishay semiconductor gave reasonable results. This device has an RDS(on) of 8 mΩ and a (Qgs1 + Qgd) of 5 nC. The estimated conduction losses are 0.115 W and the switching losses are 0.276 W. This gives a total estimated power loss of 0.391 W versus 0.6 W for our initial boundary condition. Note this does not include gate losses of approximately 71 mW and output losses of 20 mW.