JAJS204S December   2005  – November 2024 TPS74401

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable, Shutdown
      2. 6.3.2 Power-Good (VQFN Package Only)
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
    5. 6.5 Programming
      1. 6.5.1 Programmable Soft-Start
      2. 6.5.2 Sequencing Requirements
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Output Noise
    2. 7.2 Typical Applications
      1. 7.2.1 Setting the TPS74401
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Using an Auxiliary Bias Rail
      3. 7.2.3 Without an Auxiliary Bias
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
        2. 7.4.1.2 Thermal Considerations
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
      2. 8.1.2 Device Nomenclature
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Evaluation Modules
        2. 8.2.1.2 Spice Models
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Typical Characteristics

At TJ = 25°C, VOUT = 1.5V, VIN = VOUT(nom) + 0.3V, VBIAS = 3.3V, IOUT = 50mA, CIN = 1μF, CBIAS = 1μF, CSS = 0.01μF, and COUT = 10μF for legacy chip and TJ = 25°C, VIN = VOUT(nom) + 0.3V, VBIAS = 5V, IOUT = 50mA, VEN = VIN, CIN = 1μF, CBIAS = 4.7μF, and COUT = 10μF for new chip, unless otherwise noted

TPS74401 Load Regulation
Legacy chip
Figure 5-1 Load Regulation
TPS74401 Load Regulation
 
Figure 5-3 Load Regulation
TPS74401 Line Regulation
Legacy chip
Figure 5-5 Line Regulation
TPS74401 VIN Dropout Voltage vs IOUT and Temperature (TJ)
Legacy chip
Figure 5-7 VIN Dropout Voltage vs IOUT and Temperature (TJ)
TPS74401 VIN Dropout Voltage vs VBIAS  – VOUT and Temperature (TJ)
 
Figure 5-9 VIN Dropout Voltage vs VBIAS  – VOUT and Temperature (TJ)
TPS74401 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
Legacy chip
Figure 5-11 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
TPS74401 VBIAS PSRR vs Frequency
Legacy chip
Figure 5-13 VBIAS PSRR vs Frequency
TPS74401 VIN PSRR vs Frequency
Legacy chip
Figure 5-15 VIN PSRR vs Frequency
TPS74401 VIN PSRR vs Frequency
Legacy chip
Figure 5-17 VIN PSRR vs Frequency
TPS74401 VIN PSRR vs VIN  – VOUT
Legacy chip
Figure 5-19 VIN PSRR vs VIN  – VOUT
TPS74401 Noise Spectral Density
Legacy chip
Figure 5-21 Noise Spectral Density
TPS74401 Noise Spectral Density
New chip
Figure 5-23 Noise Spectral Density
TPS74401 BIAS Pin Current vs
                        Output Current and Temperature (TJ)
New chip, VIN = 1.1V, VOUT = 0.8V
Figure 5-25 BIAS Pin Current vs Output Current and Temperature (TJ)
TPS74401 BIAS Pin Current vs
                            VBIAS and Temperature (TJ)
New chip
Figure 5-27 BIAS Pin Current vs VBIAS and Temperature (TJ)
TPS74401 Soft-Start Charging
                        Current (ISS) vs Temperature
Legacy chip
Figure 5-29 Soft-Start Charging Current (ISS) vs Temperature
TPS74401 Low-Level PG Voltage vs
                        PG Current
Legacy chip
Figure 5-31 Low-Level PG Voltage vs PG Current
TPS74401 Load Transient Response
Legacy chip
Figure 5-33 Load Transient Response
TPS74401 VBIAS Line
                        Transient (3A)
Legacy chip
Figure 5-35 VBIAS Line Transient (3A)
TPS74401 VIN Line
                        Transient (3A)
Legacy chip
Figure 5-37 VIN Line Transient (3A)
TPS74401 Turn-On Response
Legacy chip
Figure 5-39 Turn-On Response
TPS74401 Power-Up, Power-Down
Legacy chip
Figure 5-41 Power-Up, Power-Down
TPS74401 Output Short-Circuit Recovery
Legacy chip
Figure 5-43 Output Short-Circuit Recovery
TPS74401 Load Regulation at Light Load
New chip
Figure 5-2 Load Regulation at Light Load
TPS74401 Load Regulation
New chip
Figure 5-4 Load Regulation
TPS74401 VIN Line Regulation
New chip
Figure 5-6 VIN Line Regulation
TPS74401 VIN Dropout Voltage vs IOUT and Temperature (TJ)
New chip
Figure 5-8 VIN Dropout Voltage vs IOUT and Temperature (TJ)
TPS74401 VIN Dropout Voltage vs VBIAS  – VOUT and Temperature (TJ)
 
Figure 5-10 VIN Dropout Voltage vs VBIAS  – VOUT and Temperature (TJ)
TPS74401 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
New chip
Figure 5-12 VBIAS Dropout Voltage vs IOUT and Temperature (TJ)
TPS74401 VBIAS PSRR vs Frequency
New chip
Figure 5-14 VBIAS PSRR vs Frequency
TPS74401 VIN PSRR vs Frequency
Legacy chip
Figure 5-16 VIN PSRR vs Frequency
TPS74401 VIN PSRR vs Frequency
New chip
Figure 5-18 VIN PSRR vs Frequency
TPS74401 VIN PSRR vs (VIN – VOUT)
New chip
Figure 5-20 VIN PSRR vs (VIN – VOUT)
TPS74401 Noise Spectral Density
Legacy chip
Figure 5-22 Noise Spectral Density
TPS74401 IBIAS vs
                        Output Current and Temperature
Legacy chip
Figure 5-24 IBIAS vs Output Current and Temperature
TPS74401 IBIAS vs
                            VBIAS and VOUT
Legacy chip
Figure 5-26 IBIAS vs VBIAS and VOUT
TPS74401 IBIAS Shutdown
                        vs Temperature
Legacy chip
Figure 5-28 IBIAS Shutdown vs Temperature
TPS74401 Soft-Start Charging
                        Current (ISS) vs Temperature (TJ)
New chip
Figure 5-30 Soft-Start Charging Current (ISS) vs Temperature (TJ)
TPS74401 Low-Level PG Voltage vs
                        Current
New chip
Figure 5-32 Low-Level PG Voltage vs Current
TPS74401 Load Transient Response
New chip
Figure 5-34 Load Transient Response
TPS74401 VBIAS Line Transient
New chip
Figure 5-36 VBIAS Line Transient
TPS74401 VIN Line Transient
New chip
Figure 5-38 VIN Line Transient
TPS74401 Turn-On Response
New chip
Figure 5-40 Turn-On Response
TPS74401 Power-Up, Power-Down
New chip
Figure 5-42 Power-Up, Power-Down