JAJS204S December   2005  – November 2024 TPS74401

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable, Shutdown
      2. 6.3.2 Power-Good (VQFN Package Only)
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
    5. 6.5 Programming
      1. 6.5.1 Programmable Soft-Start
      2. 6.5.2 Sequencing Requirements
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Output Noise
    2. 7.2 Typical Applications
      1. 7.2.1 Setting the TPS74401
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Using an Auxiliary Bias Rail
      3. 7.2.3 Without an Auxiliary Bias
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
        2. 7.4.1.2 Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
      2. 8.1.2 Device Nomenclature
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Evaluation Modules
        2. 8.2.1.2 Spice Models
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.4.1 Layout Guidelines

An excellent layout greatly improves transient performance, PSRR, and noise. To minimize the voltage droop on the input of the device during load transients, connect the capacitance on IN and BIAS as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can therefore improve stability. To achieve peak transient performance and accuracy, connect the top side of R1 in Figure 7-1 as close as possible to the load. This connection minimizes the voltage droop on BIAS during transient conditions and can improve the turn-on response.