JAJS204S December   2005  – November 2024 TPS74401

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable, Shutdown
      2. 6.3.2 Power-Good (VQFN Package Only)
      3. 6.3.3 Internal Current Limit
      4. 6.3.4 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
    5. 6.5 Programming
      1. 6.5.1 Programmable Soft-Start
      2. 6.5.2 Sequencing Requirements
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Output Noise
    2. 7.2 Typical Applications
      1. 7.2.1 Setting the TPS74401
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Using an Auxiliary Bias Rail
      3. 7.2.3 Without an Auxiliary Bias
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Power Dissipation
        2. 7.4.1.2 Thermal Considerations
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
      2. 8.1.2 Device Nomenclature
    2. 8.2 Device Support
      1. 8.2.1 Development Support
        1. 8.2.1.1 Evaluation Modules
        2. 8.2.1.2 Spice Models
    3. 8.3 ドキュメントの更新通知を受け取る方法
    4. 8.4 サポート・リソース
    5. 8.5 Trademarks
    6. 8.6 静電気放電に関する注意事項
    7. 8.7 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

at VEN = 1.1V, VIN = VOUT + 0.3V, CBIAS = 0.1μF, CIN = COUT = 10μF, IOUT = 50mA, VBIAS = 5.0V, and TJ = –40°C to 125°C, (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range VOUT + VDO 5.5 V
VBIAS BIAS pin voltage range 2.375 5.25 V
VREF Internal reference (Adjustable) TA = +25°C 0.796 0.8 0.804 V
VOUT Output voltage range VIN = 5V, IOUT = 1.5A, VBIAS = 5V VREF 3.6 V
VOUT Accuracy 2.97V ≤ VBIAS ≤ 5.25V, VOUT + 1.62V ≤ VBIAS, 50mA ≤ IOUT ≤ 3.0A(1) (legacy chip) –1 ±0.2 1 %
VOUT + VDO BIAS ≤ VBIAS ≤ 5.25 V, 100 mA ≤ IOUT ≤ I VDO BIAS , VQFN(2) –1 ±0.2 1
2.97V ≤ VBIAS ≤ 5.25V, VOUT + 1.62V ≤ VBIAS, 50mA ≤ IOUT ≤ 3.0A(1) (new chip) –1 ±0.3 1
ΔVOUT(ΔVIN) Line regulation VOUT(nom) + 0.3 ≤ VIN ≤ 5.5V VQFN (legacy chip) 0.0005 0.05 %/V
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5V DDPAK (legacy chip) 0.0005 0.06
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5V (new chip) 0.001 0.05
ΔVOUT(ΔIOUT) Load regulation 0mA ≤ IOUT ≤ 50mA (legacy chip) 0.013 %/mA
50mA ≤ IOUT ≤ 3A (legacy chip) 0.03 %/A
0mA ≤ IOUT ≤ 50mA (new chip) 0.09
50mA ≤ IOUT ≤ 3A (new chip) 0.09 %/mA
VDO VIN dropout voltage(3) IOUT = 3A, VBIAS – VOUT(nom) ≥ 1.62V, VQFN (legacy chip) 115 195 mV
IOUT = 3A, VBIAS – VOUT(nom) ≥ 1.62V, DDPAK(legacy chip) 120 240 mV
IOUT = 3 A, VBIAS – VOUT(nom) ≥ 1.62V, VQFN (new chip) 120 200 mV
VBIAS dropout voltage(3) IOUT = 3A, VIN = VBIAS  1.62 V
IOUT = 1A  1.35 V
IOUT = 500mA  1.27 V
IOUT = 100mA  1.16 V
ICL Current limit VOUT = 80% × VOUT(nom), VQFN (legacy chip) 3.8 6 A
VOUT = 80% × VOUT(nom), DDPAK (legacy chip only) 3.5 6
VOUT = 80% × VOUT(nom) (new chip) 3.9 5.5
IBIAS BIAS pin current IOUT = 0mA to 3.0 A  2 4 mA
ISHDN Shutdown supply current (IGND) VEN ≤ 0.4V  1 100 µA
IFB Feedback pin current(4) IOUT = 50mA to 3A  –250 95 250 nA
PSRR Power-supply rejection (VIN to VOUT) 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (legacy chip) 73 dB
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (new chip) 60
800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (legacy chip) 42
800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (new chip) 30
Power-supply rejection (VBIAS to VOUT) 1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (legacy chip) 62
1kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (New Chip) 57
800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (legacy chip) 50
800kHz, IOUT = 1.5A, VIN = 1.8V, VOUT = 1.5V (new chip) 45
Vn Output noise voltage 100 Hz to 100 kHz, IOUT = 1.5A, CSS = 0.001 µF (legacy chip) 16 μVrms x Vout
100 Hz to 100 kHz, IOUT = 3A, CSS = 1 nF (new chip) 20
VTRAN %VOUT droop during load transient IOUT = 100mA to 3.0A at 1A/µs, COUT = 0µF (legacy chip) 4 %VOUT
IOUT = 100mA to 3.0A at 1A/µs, COUT =2.2µF (new chip) 5
tSTR Minimum start-up time IOUT = 1.5A, CSS = open (legacy chip) 100 µs
RLOAD for IOUT = 1.0A, CSS = open (new chip) 250 µs
ISS Soft-start charging current VSS = 0.4V, IOUT = 0mA (legacy chip) 500 730 1000 nA
VSS = 0.4V, IOUT = 0mA (new chip) 300 530 800 nA
VEN(hi) Enable input high level 1.1 5.5 V
VEN(lo) Enable input low level 0 0.4 V
VEN(hys) Enable pin hysteresis 50 mV
VEN(dg) Enable pin deglitch time 20 µs
IEN Enable pin current VEN = 5V  0.1 1 µA
VIT PG trip threshold VOUT decreasing (legacy chip) 86.5 90 93.5 %VOUT
VOUT decreasing (new chip) 85 90 94 %VOUT
VHYS PG trip hysteresis 3 %VOUT
VPG(lo) PG output low voltage IPG = 1mA (sinking), VOUT < VIT  0.3 V
IPG(lkg) PG leakage current VPG = 5.25V, VOUT > VIT  0.03 1 µA
TJ Operating junction temperature –40 125 ℃
TSD Thermal shutdown temperature Shutdown, temperature increasing (legacy chip) 155 ℃
Shutdown, temperature increasing (new chip) 165 ℃
Reset, temperature decreasing 140 ℃
RPULLDOWN VBIAS = 5V, VEN = 0V New chip only 0.83 kΩ
(1) Devices tested at 0.8V; external resistor tolerance is not taken into account.
(2) VOUT is set to 1.5V to avoid minimum VBIAS restrictions.
(3) Dropout is defined as the voltage from VIN to VOUT when VOUT is 2% below nominal
(4) IFB current flow is out of the device.