Connect a low ESR ceramic bypass capacitor to the VIN pin. Care must be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the TPS5410 ground pin. The best way to do this is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7μF ceramic with a X5R or X7R dielectric.

There must be a ground area on the top layer directly underneath the IC to connect the GND pin of the device and the anode of the catch diode. Tie the GND pin to the PCB ground by connecting it to the ground area under the device as shown in Figure 7-17.

Route the PH pin to the output inductor, catch diode and boot capacitor. Because the PH connection is the switching node, the inductor must be located close to the PH pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The catch diode must also be placed close to the device to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component placements and connections shown work well, but other connection routings can also be effective.

Connect the output filter capacitors as shown between the VOUT trace and GND. Keep the loop formed by the PH pin, Lout, Cout and GND as small as is practical.

Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not route this trace too close to the PH trace. Due to the size of the IC package and the device pinout, the trace can must be routed under the output capacitor. The routing can be done on an alternate layer if a trace under the output capacitor is not desired.

If the grounding scheme shown is used through a connection to a different layer to route to the ENA pin.