JAJS398F January 2009 – April 2018 DAC7568 , DAC8168 , DAC8568
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t1 | SCLK falling edge to SYNC falling edge (for successful write operation) | AVDD = 2.7V to 5.5V | 10 | ns | ||
t2(3) | SCLK cycle time | AVDD = 2.7V to 5.5V | 20 | ns | ||
t3 | SYNC rising edge to 31st SCLK falling edge (for successful SYNC interrupt) | AVDD = 2.7V to 5.5V | 13 | ns | ||
t4 | Minimum SYNC HIGH time | AVDD = 2.7V to 5.5V | 80 | ns | ||
t5 | SYNC to SCLK falling edge setup time | AVDD = 2.7V to 5.5V | 13 | ns | ||
t6 | SCLK LOW time | AVDD = 2.7V to 5.5V | 8 | ns | ||
t7 | SCLK HIGH time | AVDD = 2.7V to 5.5V | 8 | ns | ||
t8 | SCLK falling edge to SYNC rising edge | AVDD = 2.7V to 5.5V | 10 | ns | ||
t9 | Data setup time | AVDD = 2.7V to 5.5V | 6 | ns | ||
t10 | Data hold time | AVDD = 2.7V to 5.5V | 4 | ns | ||
t11 | SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode | AVDD = 2.7V to 5.5V | 40 | ns | ||
t12 | LDAC pulse width LOW time | AVDD = 2.7V to 5.5V | 80 | ns | ||
t13 | LDAC falling edge to SCLK falling edge for synchronous LDAC update mode | AVDD = 2.7V to 5.5V | 4 × t1 | ns | ||
t14 | 32nd SCLK falling edge to LDAC rising edge | AVDD = 2.7V to 5.5V | 40 | ns | ||
t15 | CLR pulse width LOW time | AVDD = 2.7V to 5.5V | 80 | ns |