JAJS398F
January 2009 – April 2018
DAC7568
,
DAC8168
,
DAC8568
PRODUCTION DATA.
1
特長
2
アプリケーション
3
概要
ブロック図
4
改訂履歴
5
概要(続き)
6
Device Comparison Table
7
Pin Configuration and Functions
Pin Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
Electrical Characteristics
8.3
Timing Requirements
8.4
Typical Characteristics: Internal Reference
8.5
Typical Characteristics: DAC at AVDD = 5.5 V
8.6
Typical Characteristics: DAC at AVDD = 3.6 V
8.7
Typical Characteristics: DAC at AVDD = 2.7 V
9
Detailed Description
9.1
Functional Block Diagram
9.2
Feature Description
9.2.1
Digital-to-Analog Converter (DAC)
9.2.2
Resistor String
9.2.3
Output Amplifier
9.2.4
Internal Reference
9.2.5
Serial Interface
9.2.6
Input Shift Register
Table 1.
DAC8568 Data Input Register Format
Table 2.
DAC8168 Data Input Register Format
Table 3.
DAC7568 Data Input Register Format
9.2.7
SYNC Interrupt
9.2.8
Power-on Reset to Zero Scale or Midscale
9.2.9
Clear Code Register and CLR Pin
9.2.10
Software Reset Function
9.2.11
Operating Examples: DAC7568/DAC8168/DAC8568
Table 4.
1st: Write to Data Buffer A:
Table 5.
2nd: Write to Data Buffer B:
Table 6.
3rd: Write to Data Buffer G:
Table 7.
4th: Write to Data Buffer H and Simultaneously Update all DACs:
Table 8.
1st: Write to Data Buffer C and Load DAC C: DAC C Output Settles to Specified Value Upon Completion:
Table 9.
2nd: Write to Data Buffer D and Load DAC D: DAC D Output Settles to Specified Value Upon Completion:
Table 10.
3rd: Write to Data Buffer E and Load DAC E: DAC E Output Settles to Specified Value Upon Completion:
Table 11.
4th: Write to Data Buffer F and Load DAC F: DAC F Output Settles to Specified Value Upon Completion:
Table 12.
1st: Write Power-Down Command to DAC Channel A and DAC Channel B: DAC A and DAC B to 1kΩ.
Table 13.
2nd: Write Power-Down Command to DAC Channel H: DAC H to 1kΩ.
Table 14.
3rd: Write Power-Down Command to DAC Channel C and DAC Channel D: DAC C and DAC D to 100kΩ.
Table 15.
4th: Write Power-Down Command to DAC Channel F: DAC F to 100kΩ.
Table 16.
1st: Write Sequence for Enabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time:
Table 17.
2nd: Write Sequence to Power-Down All DACs to High-Impedance:
Table 18.
1st: Write Sequence for Disabling the DAC7568, DAC8168, and DAC8568 Internal Reference All the Time (after this sequence, these devices require an external reference source to function):
Table 19.
2nd: Write Sequence to Write Specified Data to All DACs:
9.3
Device Functional Modes
9.3.1
Enable/Disable Internal Reference
9.3.1.1
Static Mode
Table 20.
Write Sequence for Enabling Internal Reference (Static Mode) (Internal Reference Powered On—08000001h)
Table 21.
Write Sequence for Disabling Internal Reference (Static Mode) (Internal Reference Powered On—08000000h)
9.3.1.2
Flexible Mode
Table 22.
Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Powered On—09080000h)
Table 23.
Write Sequence for Enabling Internal Reference (Flexible Mode) (Internal Reference Always Powered On—090A0000h)
Table 24.
Write Sequence for Disabling Internal Reference (Flexible Mode) (Internal Reference Always Powered Down—090C0000h)
Table 25.
Write Sequence for Switching from Flexible Mode to Static Mode for Internal Reference (Internal Reference Always Powered Down—09000000h)
9.3.2
LDAC Functionality
9.3.3
Power-Down Modes
9.3.3.1
DAC Power-Down Commands
10
Application and Implementation
10.1
Application Information
10.2
Typical Applications - Microprocessor Interfacing
10.2.1
DAC7568/DAC8168/DAC8568 to an 8051 Interface
10.2.1.1
Detailed Design Procedure
10.2.1.1.1
Internal Reference
10.2.1.1.1.1
Supply Voltage
10.2.1.1.1.2
Temperature Drift
10.2.1.1.1.3
Noise Performance
10.2.1.1.1.4
Load Regulation
10.2.1.1.1.5
Long-Term Stability
10.2.1.1.1.6
Thermal Hysteresis
10.2.1.1.2
DAC Noise Performance
10.2.1.1.3
Bipolar Operation Using The DAC7568/DAC8168/DAC8568
10.2.2
DAC7568/DAC8168/DAC8568 to Microwire Interface
10.2.3
DAC7568/DAC8168/DAC8568 to 68HC11 Interface
11
Layout
11.1
Layout Guidelines
12
デバイスおよびドキュメントのサポート
12.1
デバイス・サポート
12.1.1
デバイスの項目表記
12.1.1.1
静的特性
12.1.1.1.1
分解能
12.1.1.1.2
最下位ビット(LSB)
12.1.1.1.3
最上位ビット(MSB)
12.1.1.1.4
相対精度または積分非直線性(INL)
12.1.1.1.5
微分非直線性(DNL)
12.1.1.1.6
フルスケール誤差
12.1.1.1.7
オフセット誤差
12.1.1.1.8
ゼロ・コード誤差
12.1.1.1.9
ゲイン誤差
12.1.1.1.10
フルスケール誤差ドリフト
12.1.1.1.11
オフセット誤差ドリフト
12.1.1.1.12
ゼロ・コード誤差ドリフト
12.1.1.1.13
ゲイン温度係数
12.1.1.1.14
電源除去率(PSRR)
12.1.1.1.15
単調性
12.1.1.2
動的特性
12.1.1.2.1
スルー・レート
12.1.1.2.2
出力電圧のセトリング時間
12.1.1.2.3
コード変化/デジタル-アナログ・グリッチ・エネルギー
12.1.1.2.4
デジタル・フィードスルー
12.1.1.2.5
チャネル間DCクロストーク
12.1.1.2.6
チャネル間ACクロストーク
12.1.1.2.7
信号対雑音比(SNR)
12.1.1.2.8
全高調波歪み(THD)
12.1.1.2.9
スプリアスフリー・ダイナミック・レンジ(SFDR)
12.1.1.2.10
信号対雑音比+歪み(SINAD)
12.1.1.2.11
DAC出力ノイズ密度
12.1.1.2.12
DAC出力ノイズ
12.1.1.2.13
フルスケール範囲(FSR)
12.2
関連リンク
12.3
ドキュメントの更新通知を受け取る方法
12.4
コミュニティ・リソース
12.5
商標
12.6
静電気放電に関する注意事項
12.7
Glossary
13
メカニカル、パッケージ、および注文情報
8.4
Typical Characteristics: Internal Reference
At T
A
= +25°C, unless otherwise noted.
Figure 2.
Internal Reference voltage vs Temperature (Grades C and D)
Figure 4.
Reference Output Temperature Drift (–40°C to +125°C, Grades C and D)
Figure 6.
Reference Output Temperature Drift (0°C to +125°C, Grades C and D)
See the
Application Information
section of this data sheet for more details.
Figure 8.
Internal Reference Noise Density vs Frequency
Figure 10.
Internal Reference Voltage vs Load Current (Grades C and D)
Figure 12.
Internal Reference Voltage vs Supply Voltage (Grades C and D)
Figure 3.
Internal Reference Voltage vs temperature (Grades A and B)
Figure 5.
Reference Output Temperature Drift (–40°C to +125°, Grades A and B)
See the
Application Information
section of this data sheet for more details.
Figure 7.
Long-Term Stability/Drift
See the
Application Information
section of this data sheet for more details.
Figure 9.
Internal Reference Noise 0.1 Hz to 10 Hz
Figure 11.
Internal Reference Voltage vs Load Current (Grades A and B)
Figure 13.
Internal Reference Voltage vs Supply Voltage (Grades A and B)