JAJS398F January 2009 – April 2018 DAC7568 , DAC8168 , DAC8568
PRODUCTION DATA.
16-PIN | 14-PIN | NAME | DESCRIPTION |
---|---|---|---|
1 | — | LDAC | Load DACs. |
2 | 1 | SYNC | Level-triggered control input (active low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock edges. The DAC output updates following the 32nd clock. If SYNC is taken high before the 31st clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC7568/DAC8168/DAC8568. Schmitt-Trigger logic input. |
3 | 2 | AVDD | Power-supply input, 2.7V to 5.5V |
4 | 3 | VOUTA | Analog output voltage from DAC A |
5 | 4 | VOUTC | Analog output voltage from DAC C |
6 | 5 | VOUTE | Analog output voltage from DAC E |
7 | 6 | VOUTG | Analog output voltage from DAC G |
8 | 7 | VREFIN/
VREFOUT |
Positive reference input / reference output 2.5V if internal reference used.(1) |
9 | — | CLR | Asynchronous clear input. |
10 | 8 | VOUTH | Analog output voltage from DAC H |
11 | 9 | VOUTF | Analog output voltage from DAC F |
12 | 10 | VOUTD | Analog output voltage from DAC D |
13 | 11 | VOUTB | Analog output voltage from DAC B |
14 | 12 | GND | Ground reference point for all circuitry on the device |
15 | 13 | DIN | Serial data input. Data are clocked into the 32-bit input shift register on each falling edge of the serial clock input. Schmitt-Trigger logic input. |
16 | 14 | SCLK | Serial clock input. Data can be transferred at rates up to 50MHz. Schmitt-Trigger logic input. |