JAJS436D December   2009  – December 2019 BQ24610 , BQ24617

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Battery Voltage Regulation
      2. 9.3.2  Battery Current Regulation
      3. 9.3.3  Input Adapter Current Regulation
      4. 9.3.4  Precharge
      5. 9.3.5  Charge Termination, Recharge, and Safety Timer
      6. 9.3.6  Power Up
      7. 9.3.7  Enable and Disable Charging
      8. 9.3.8  System Power Selector
      9. 9.3.9  Automatic Internal Soft-Start Charger Current
      10. 9.3.10 Converter Operation
      11. 9.3.11 Synchronous and Nonsynchronous Operation
      12. 9.3.12 Cycle-by-Cycle Charge Undercurrent Protection
      13. 9.3.13 Input Overvoltage Protection (ACOV)
      14. 9.3.14 Input Undervoltage Lockout (UVLO)
      15. 9.3.15 Battery Overvoltage Protection
      16. 9.3.16 Cycle-by-Cycle Charge Overcurrent Protection
      17. 9.3.17 Thermal Shutdown Protection
      18. 9.3.18 Temperature Qualification
      19. 9.3.19 Timer Fault Recovery
      20. 9.3.20 PG Output
      21. 9.3.21 CE (Charge Enable)
      22. 9.3.22 Charge Status Outputs
      23. 9.3.23 Battery Detection
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 System with Power Path
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Inductor Selection
          2. 10.2.1.2.2 Input Capacitor
          3. 10.2.1.2.3 Output Capacitor
          4. 10.2.1.2.4 Power MOSFETs Selection
          5. 10.2.1.2.5 Input Filter Design
          6. 10.2.1.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
        3. 10.2.1.3 Application Curves
      2. 10.2.2 Simplified System without Power Path or DPM
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curves
      3. 10.2.3 Lead-Acid Charging System
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
        3. 10.2.3.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 デバイス・サポート
      1. 13.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 13.2 関連リンク
    3. 13.3 ドキュメントの更新通知を受け取る方法
    4. 13.4 サポート・リソース
    5. 13.5 商標
    6. 13.6 静電気放電に関する注意事項
    7. 13.7 Glossary
  14. 14メカニカル、パッケージ、および注文情報

9.3.20 PG Output

The open-drain PG (power-good) output indicates whether the VCC voltage is valid or not. The open-drain FET turns on whenever BQ2461x has a valid VCC input (not in UVLO or ACOV or SLEEP mode). The PGpin can be used to drive an LED or communicate to the host processor.