JAJS467F December   2008  – April 2019 TPS61175

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Switching Frequency
      2. 7.3.2 Soft Start
      3. 7.3.3 Overcurrent Protection
      4. 7.3.4 Enable and Thermal Shutdown
      5. 7.3.5 Undervoltage Lockout (UVLO)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Minimum ON Time and Pulse Skipping
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Custom Design with WEBENCH Tools
        2. 8.2.2.2  Determining the Duty Cycle
        3. 8.2.2.3  Selecting the Inductor
        4. 8.2.2.4  Computing the Maximum Output Current
        5. 8.2.2.5  Setting Output Voltage
        6. 8.2.2.6  Setting the Switching Frequency
        7. 8.2.2.7  Setting the Soft-Start Time
        8. 8.2.2.8  Selecting the Schottky Diode
        9. 8.2.2.9  Selecting the Input and Output Capacitors
        10. 8.2.2.10 Compensating the Small Signal Control Loop
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
    2. 11.2 開発サポート
      1. 11.2.1 WEBENCHツールによるカスタム設計の作成
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

7.1 Overview

The TPS61175 integrates a 40-V low-side switch FET for up to 38-V output. The device regulates the output with current mode pulse width modulation (PWM) control. The PWM control circuitry turns on the switch at the beginning of each switching cycle. The input voltage is applied across the inductor and stores the energy as inductor current ramps up. During this portion of the switching cycle, the load current is provided by the output capacitor. When the inductor current rises to the threshold set by the error amplifier output, the power switch turns off and the external Schottky diode is forward biased. The inductor transfers stored energy to replenish the output capacitor and supply the load current. This operation repeats each every switching cycle. As shown in Functional Block Diagram, the duty cycle of the converter is determined by the PWM control comparator which compares the error amplifier output and the current signal. The switching frequency is programmed by the external resistor or synchronized to an external clock signal.

A ramp signal from the oscillator is added to the current ramp to provide slope compensation. Slope compensation is necessary to avoid subharmonic oscillation that is intrinsic to the current mode control at duty cycle higher than 50%. If the inductor value is lower than 4.7 μH, the slope compensation may not be adequate.

The feedback loop regulates the FB pin to a reference voltage through a transconductance error amplifier. The output of the error amplifier is connected to the COMP pin. An external RC compensation network is connected to the COMP pin to optimize the feedback loop for stability and transient response.