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  • ADS79xx ピン互換、12/10/8ビット、1MSPS、16/12/8/4チャネル、シングルエンド、シリアル・インターフェイスADC

    • JAJS503C June   2008  – July 2018 ADS7950 , ADS7951 , ADS7952 , ADS7953 , ADS7954 , ADS7955 , ADS7956 , ADS7957 , ADS7958 , ADS7959 , ADS7960 , ADS7961

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  • ADS79xx ピン互換、12/10/8ビット、1MSPS、16/12/8/4チャネル、シングルエンド、シリアル・インターフェイスADC
  1. 1 特長
  2. 2 アプリケーション
    1.     詳細ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TSSOP Packages
    2.     Pin Functions: VQFN Packages
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TSSOP
    5. 7.5  Thermal Information: VQFN
    6. 7.6  Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953
    7. 7.7  Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957
    8. 7.8  Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics (All ADS79xx Family Devices)
    11. 7.11 Typical Characteristics (12-Bit Devices Only)
    12. 7.12 Typical Characteristics (12-Bit Devices Only)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Power Saving
    4. 8.4 Device Functional Modes
      1. 8.4.1 Channel Sequencing Modes
      2. 8.4.2 Device Programming and Mode Control
        1. 8.4.2.1 Mode Control Register
        2. 8.4.2.2 Program Registers
      3. 8.4.3 Device Power-Up Sequence
      4. 8.4.4 Operating in Manual Mode
      5. 8.4.5 Operating in Auto-1 Mode
      6. 8.4.6 Operating in Auto-2 Mode
      7. 8.4.7 Continued Operation in a Selected Mode
    5. 8.5 Programming
      1. 8.5.1 Digital Output
      2. 8.5.2 GPIO Registers
      3. 8.5.3 Alarm Thresholds for GPIO Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
    2. 9.2 Typical Applications
      1. 9.2.1 Unbuffered Multiplexer Output (MXO)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 OPA192 Buffered Multiplexer Output (MXO)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報
  14. 重要なお知らせ
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DATA SHEET

ADS79xx ピン互換、12/10/8ビット、1MSPS、16/12/8/4チャネル、シングルエンド、シリアル・インターフェイスADC

このリソースの元の言語は英語です。 翻訳は概要を便宜的に提供するもので、自動化ツール (機械翻訳) を使用していることがあり、TI では翻訳の正確性および妥当性につきましては一切保証いたしません。 実際の設計などの前には、ti.com で必ず最新の英語版をご参照くださいますようお願いいたします。

1 特長

  • サンプル・レート1MHzのシリアル・デバイス
  • 分解能12/10/8ビットの製品ファミリ
  • ゼロ・レイテンシ
  • 20MHzのシリアル・インターフェイス
  • アナログ電源電圧範囲: 2.7～5.25V
  • I/O電源電圧範囲: 1.7～5.25V
  • ソフトウェアで2種類のユニポーラ入力レンジを選択可能: 0～VREFおよび0～2×VREF
  • 自動および手動モードによるチャネル選択
  • 4/8チャネル版と12/16チャネル版でそれぞれ共通のフットプリント
  • チャネルごとに2つのアラーム・レベルを設定可能
  • TSSOPパッケージでは4本、VQFNパッケージでは1本のGPIOを個別に設定可能
  • 消費電力(標準値): 1MSPS時14.5mW (＋VA＝5V、＋VBD＝3V)
  • パワーダウン電流(1µA)
  • 入力帯域幅(3dB時47MHz)
  • 38/30ピンTSSOPパッケージと32/24ピンVQFNパッケージ

2 アプリケーション

  • PLC/IPC
  • 光ライン・カード監視
  • 医療用計測機器
  • デジタル電源
  • マルチチャネル汎用信号監視
  • 高速データ収集システム
  • 高速閉ループ・システム

詳細ブロック図

ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 fbd_fp_sbas652.gif

3 概要

ADS79xxは、12/10/8ビットのピン互換マルチチャネル・アナログ/デジタル・コンバータ・ファミリです。デバイス比較表に、この製品ファミリに属する12のデバイスをすべて示しています。

このファミリのデバイスは、サンプル・アンド・ホールド機能を内蔵した、電荷再分配方式の逐次比較型(SAR) A/Dコンバータです。

2.7V～5.25Vという広いアナログ電源電圧範囲に対応し、消費電力が極めて低いことから、バッテリ駆動機器や絶縁型電源といった用途に最適です。

1.7V～5.25Vの広いI/O電源電圧範囲により、最もよく使用されるデジタル・ホストとのグルーレス・インターフェイスを容易に実現できます。シリアル・インターフェイスはCSおよびSCLKによって制御され、マイクロプロセッサやDSPと容易に接続できます。

入力信号はCSの立ち下がりエッジでサンプリングされます。変換、シリアル・データ出力、シリアル・データ入力の読み取りには、SCLKを使用します。事前に選択したチャネルの自動切り替えを実行したり、新しい変換サイクルのチャネルを手動で選択することも可能です。

ソフトウェアで2つの入力レンジ(0V～VREFおよび0V～2×VREF)を選択でき、GPIO (TSSOPパッケージは4本、VQFNパッケージは1本)を個別に設定できるほか、チャネルごとに2つのアラーム・スレッショルドを設定可能です。このような特長から、ほとんどのデータ収集機器に適合します。

また、優れたパワーダウン機能を備えており、低速変換動作時の消費電力の削減に極めて有効です。

このファミリの16/12チャネル版は38ピンTSSOPおよび32ピンVQFNパッケージで供給され、4/8チャネル版は30ピンTSSOPおよび24ピンVQFNパッケージで供給されます。

製品情報(1)

型番 パッケージ 本体サイズ（公称）
ADS79xx TSSOP (30) 7.80mm×4.40mm
VQFN (24) 4.00mm×4.00mm
TSSOP (38) 9.70mm×4.40mm
VQFN (32) 5.00mm×5.00mm
  1. 利用可能なすべてのパッケージについては、このデータシートの末尾にある注文情報を参照してください。

4 改訂履歴

Changes from B Revision (July 2015) to C Revision

  • Changed 「特長」の入力レンジで0～2.5Vおよび0～5Vを0～VREFおよび0～2×VREFにGo
  • Changed 「特長」のGPIOGo
  • Changed 「アプリケーション」の光ライン・カード監視およびマルチチャネル汎用信号監視Go
  • Changed 「概要」セクションで(0V～2.5Vおよび0V～5V)を(0V～VREFおよび0V～2×VREF)にGo
  • Deleted 製品比較表Go
  • Changed RGE to RHB for two 32-pin VQFN pin diagrams Go
  • Added 30-pin DBT package Go
  • Changed I/O column of Pin Functions: TSSOP Packages table to show full definition instead of abbreviationGo
  • Added active low to definition of CS pin in Pin Functions: TSSOP Packages tableGo
  • Changed pin name and description of Alarm pin in Pin Functions: TSSOP Packages table Go
  • Added settings to description of Range pin in Pin Functions: TSSOP Packages table: added (1) to high and (0) to lowGo
  • Added active low to description of CS pin in Pin Functions: VQFN Packages tableGo
  • Changed pin name and description of Alarm pin in Pin Functions: VQFN Packages table Go
  • Changed value of Input current to any pin except supply pins row from ±10 mA (max) to –10 mA (min) and 10 mA (max) in Absolute Maximum Ratings tableGo
  • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statementGo
  • Changed minimum specification from –1 LSB to –0.99 LSB in first row of Differential linearity parameterGo
  • Added input to Reference input resistance parameter nameGo
  • Changed maximum specification from FFC Hex to 4092 LSB in Alarm Setting parameters Go
  • Changed unit from Numbers to Conversion in Invalid conversions after power up or reset parameter Go
  • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statement Go
  • Added input to Reference input resistance parameter name Go
  • Changed maximum specification from FFC Hex to 4092 LSB in Alarm Setting parameters Go
  • Changed VBD = 1.7 V to 5.25 V to VBD = 1.7 V to +VA in condition statement Go
  • Added input to Reference input resistance parameter name Go
  • Changed maximum specification from FF Hex to 255 LSB in Alarm Setting parameters Go
  • Changed unit from Numbers to Conversion in Invalid conversions after power up or reset parameter Go
  • Changed REF and GND pins to REFP and REFM pins in the Reference section Go
  • Added Example Manual Mode Timing Diagram figure and corresponding text to Operating in Manual Mode section Go
  • Added Example Auto-1 Mode Timing Diagram figure and corresponding text to the Operating in Auto-1 Mode section Go
  • Added Example Auto-2 Mode Timing Diagram figure and corresponding text to the Operating in Auto-2 Mode section Go
  • Changed 2.5V to VREF in first DI06 row and 5V to 2xVREF in second DI06 rowGo
  • Changed binary code from 0001 1111 1111 to 0011 1111 1111 in Full scale row of Ideal Input Voltages for 10-Bit Devices and Digital Output Codes for 10-Bit Devices (ADS7954/55/56/57) tableGo
  • Changed 10-Bit to 8-Bit in title of Ideal Input Voltages for 8-Bit Devices and Digital Output Codes for 8-Bit Devices (ADS7958/59/60/61) tableGo
  • Changed Application Diagram for an Unbuffered MXO figure note Go
  • Changed Recommended Layout figure title to Recommended Layout for the TSSOP Packaged DeviceGo
  • Added Recommended Layout for the VQFN Packaged Device figureGo

Changes from A Revision (April 2010) to B Revision

  • Added 「ESD定格」の表、「機能説明」セクション、「デバイスの機能モード」、「アプリケーションと実装」セクション、「電源に関する推奨事項」セクション、「レイアウト」セクション、「デバイスおよびドキュメントのサポート」セクション、「メカニカル、パッケージ、および注文情報」セクションGo

Changes from * Revision (June 2008) to A Revision

  • Added QFN情報を「特長」にGo
  • Added QFN情報を「概要」にGo
  • Changed VEE to AGND and VCC to +VA on 38-pin TSSOP pinoutGo
  • Added QFN pinoutGo
  • Added QFN pinoutGo
  • Added QFN pinoutGo
  • Added QFN pinoutGo
  • Added terminal functions for QFN packagesGo
  • Changed ADS7950/4/8 QFN package MXO pin from 7 to 3Go
  • Added VREF = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7950/51/52/53Go
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Added while 2VREF ≤ +VA to Absolute input range span range 2 test conditionsGo
  • Added Total unadjusted error (TUE) specificationGo
  • Changed reference voltage at REFP min and max valuesGo
  • Added Note to Electrical Characteristics, ADS7950/51/52/53 Go
  • Added VREF = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7954/55/56/57 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 VGo
  • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 VGo
  • Added Vref = 2.5 V ± 0.1 V to Electrical Characteristics, ADS7958/59/60/61 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Added while 2VREF ≤ +VA to full-scale input span range 2 test conditionsGo
  • Changed Vref reference voltage at REFP min value from 2.49 V to 2.0 VGo
  • Changed Vref reference voltage at REFP max value from 2.51 V to 3.0 VGo
  • Changed tsu1 values from max to minGo
  • Changed tsu2 values from max to minGo
  • Added TOTAL UNADJUSTED ERROR (TUE Max) graphGo
  • Added TOTAL UNADJUSTED ERROR (TUE Min) graphGo
  • Changed GPIO pins descriptionGo
  • Added device powerdown through GPIO in the case of the TSSOP packaged devicesGo
  • Added note to Table 1Go
  • Added note to Table 2Go
  • Added note to Table 5Go
  • Added note to Programming GPIO Registers descriptionGo
  • Added QFN information to Table 11Go
  • Changed DI12 = 1? from No or No to Yes or No in Figure 59Go
  • Added note to Figure 60Go

5 デバイス比較表

チャネル数 分解能
12ビット 10ビット 8ビット
16 ADS7953 ADS7957 ADS7961
12 ADS7952 ADS7956 ADS7960
8 ADS7951 ADS7955 ADS7959
4 ADS7950 ADS7954 ADS7958

6 Pin Configuration and Functions


DBT Package
38-Pin TSSOP
Top View
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 tssop38_SLAS605C.gif
DBT Package
30-Pin TSSOP
Top View
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 tssop30_SLAS605C.gif
RHB Package
32-Pin VQFN
Top View
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 pos3_las605.gif

RHB Package
32-Pin VQFN
Top View
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 pos4_las605.gif
RGE Package
24-Pin VQFN
Top View
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 pos5_las605.gif
RGE Package
24-Pin VQFN
Top View
ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 pos6_las605.gif

Pin Functions: TSSOP Packages

PIN I/O DESCRIPTION
NAME ADS7953
ADS7957
ADS7961		 ADS7952
ADS7956
ADS7960		 ADS7951
ADS7955
ADS7959		 ADS7950
ADS7954
ADS7958
REFERENCE
REFP 4 4 4 4 Analog input Reference input
REFM 3 3 3 3 Analog input Reference ground
ADC ANALOG INPUT
AINP 8 8 8 8 Analog input ADC input signal
AINM 9 9 9 9 Analog input ADC input ground
MULTIPLEXER
MXO 7 7 7 7 Analog output Multiplexer output
Ch0 28 28 20 20 Analog input Analog channel for multiplexer
Ch1 27 27 19 18 Analog input Analog channel for multiplexer
Ch2 26 26 18 14 Analog input Analog channel for multiplexer
Ch3 25 25 17 12 Analog input Analog channel for multiplexer
Ch4 24 24 14 — Analog input Analog channel for multiplexer
Ch5 23 23 13 — Analog input Analog channel for multiplexer
Ch6 22 22 12 — Analog input Analog channel for multiplexer
Ch7 21 21 11 — Analog input Analog channel for multiplexer
Ch8 18 18 — — Analog input Analog channel for multiplexer
Ch9 17 17 — — Analog input Analog channel for multiplexer
Ch10 16 16 — — Analog input Analog channel for multiplexer
Ch11 15 15 — — Analog input Analog channel for multiplexer
Ch12 14 — — — Analog input Analog channel for multiplexer
Ch13 13 — — — Analog input Analog channel for multiplexer
Ch14 12 — — — Analog input Analog channel for multiplexer
Ch15 11 — — — Analog input Analog channel for multiplexer
DIGITAL CONTROL SIGNALS
CS 31 31 23 23 Digital input Chip-select input pin; active low
SCLK 32 32 24 24 Digital input Serial clock input pin
SDI 33 33 25 25 Digital input Serial data input pin
SDO 34 34 26 26 Digital output Serial data output pin
GENERAL-PURPOSE INPUTS/OUTPUTS(1)
GPIO0 37 37 29 29 Digital I/O General-purpose input or output
Alarm Digital output Active high alarm output. For configuration, see the Programming section.
GPIO1 38 38 30 30 Digital I/O General-purpose input or output
Low alarm Digital output Active high output indicating low alarm
GPIO2 1 1 1 1 Digital I/O General-purpose input or output
Range Digital input Selects ADC input range: High (1) -> Range 2 (0 to 2xVREF) / Low (0) -> Range 1 (0 to VREF)
GPIO3 2 2 2 2 Digital I/O General-purpose input or output
PD Digital input Active low power-down input
POWER SUPPLY AND GROUND
+VA 5, 29 5, 29 5, 21 5, 21 — Analog power supply
AGND 6, 10, 19, 20, 30 6, 10, 19, 20, 30 6, 10, 22 6, 10, 22 — Analog ground
+VBD 36 36 28 28 — Digital I/O supply
BDGND 35 35 27 27 — Digital ground
NC PINS
— — 11, 12, 13, 14 15, 16 11, 13, 15, 16, 17, 19 — Pins internally not connected, do not float these pins, connect these pins to ground
(1) These pins have programmable dual functionality. See Table 12 for functionality programming.

Pin Functions: VQFN Packages

PIN I/O DESCRIPTION
PIN NAME ADS7953
ADS7957
ADS7961		 ADS7952
ADS7956
ADS7960		 ADS7951
ADS7955
ADS7959		 ADS7950
ADS7954
ADS7958
REFERENCE
REFP 31 31 24 24 Analog input Reference input
REFM 30 30 23 23 Analog input Reference ground
ADC ANALOG INPUT
AINP 3 3 4 4 Analog input ADC input signal
AINM 4 4 5 5 Analog input ADC input ground
MULTIPLEXER
MXO 2 2 3 3 Analog output Multiplexer output
Ch0 20 18 13 11 Analog input Analog-input channel for multiplexer
Ch1 19 17 12 10 Analog input Analog-input channel for multiplexer
Ch2 18 16 11 9 Analog input Analog-input channel for multiplexer
Ch3 17 15 10 8 Analog input Analog-input channel for multiplexer
Ch4 16 14 9 — Analog input Analog-input channel for multiplexer
Ch5 15 13 8 — Analog input Analog-input channel for multiplexer
Ch6 14 12 7 — Analog input Analog-input channel for multiplexer
Ch7 13 11 6 — Analog input Analog-input channel for multiplexer
Ch8 12 10 — — Analog input Analog-input channel for multiplexer
Ch9 11 9 — — Analog input Analog-input channel for multiplexer
Ch10 10 8 — — Analog input Analog-input channel for multiplexer
Ch11 9 7 — — Analog input Analog-input channel for multiplexer
Ch12 8 — — — Analog input Analog-input channel for multiplexer
Ch13 7 — — — Analog input Analog-input channel for multiplexer
Ch14 6 — — — Analog input Analog-input channel for multiplexer
Ch15 5 — — — Analog input Analog-input channel for multiplexer
DIGITAL CONTROL SIGNALS
CS 23 23 16 16 Digital input Chip-select input pin; active low
SCLK 24 24 17 17 Digital input Serial clock input pin
SDI 25 25 18 18 Digital input Serial data input pin
SDO 26 26 19 19 Digital output Serial data output pin
GENERAL-PURPOSE INPUT/OUTPUT(1)
GPIO0 29 29 22 22 Digital I/O General purpose input or output
Alarm Digital output Active high alarm output. For configuration, see the Programming section.
POWER SUPPLY AND GROUND
+VA 21, 32 21, 32 1, 14 1, 14 — Analog power supply
AGND 1, 22 1, 22 2, 15 2, 15 — Analog ground
+VBD 28 28 21 21 — Digital I/O supply
BDGND 27 27 20 20 — Digital ground
NC PINS
— — 5, 6, 19, 20 — 6, 7, 12, 13 — Pins internally not connected, do not float these pins, connect these pins to ground
(1) This pin has programmable dual functionality. See Table 12 for functionality programming.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
AINP or CHn to AGND –0.3 VA +0.3 V
+VA to AGND, +VBD to BDGND –0.3 7 V
Digital input voltage to BDGND –0.3 7 V
Digital output to BDGND –0.3 VA + 0.3 V
Input current to any pin except supply pins –10 10 mA
Operating temperature –40 125 °C
Junction temperature (TJ Max) 150 °C
Storage temperature (Tstg) –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) DBT packaged versions of ADS79xx family devices are rated for MSL2 260°C per the JSTD-020 specifications and the RGE and RHB packaged versions of ADS79xx family devices are rated for MSL3 260C per JSTD-020 specifications

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V(+VA) Analog power-supply voltage 2.7 3.3 5.25 V
V(+VBD) Digital I/O-supply voltage 1.7 3.3 V(+VA) V
V(REF) Reference voltage 2 2.5 3 V
ƒ(SCLK) SCLK frequency 20 MHz
TA Operating temperature range –40 125 °C

7.4 Thermal Information: TSSOP

THERMAL METRIC(1) ADS795x UNIT
DBT (TSSOP) DBT (TSSOP)
38 PINS 30 PINS
RθJA Junction-to-ambient thermal resistance 83.6 89.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 29.8 22.9 °C/W
RθJB Junction-to-board thermal resistance 44.7 43.1 °C/W
ψJT Junction-to-top characterization parameter 2.9 0.8 °C/W
ψJB Junction-to-board characterization parameter 44.1 42.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Thermal Information: VQFN

THERMAL METRIC(1) ADS7953, ADS7957, ADS7961 UNIT
RHB (VQFN) RGE (VQFN)
32 PINS 24 PINS
RθJA Junction-to-ambient thermal resistance 40.6 36.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 32.1 39.3 °C/W
RθJB Junction-to-board thermal resistance 13.1 14.7 °C/W
ψJT Junction-to-top characterization parameter 0.8 0.7 °C/W
ψJB Junction-to-board characterization parameter 13 14.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.7 5.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.6 Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953

VA = 2.7 V to 5.25 V, VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span(1) Range 1 0 VREF V
Range 2 while 2xVREF ≤ +VA 0 2*VREF
Absolute input range Range 1 –0.2 VREF + 0.2 V
Range 2 while 2xVREF ≤ +VA –0.2 2*VREF + 0.2
Input capacitance 15 pF
Input leakage current TA = 125°C 61 nA
SYSTEM PERFORMANCE
Resolution 12 Bits
No missing codes ADS795XSB(2) 12 Bits
ADS795XS(2) 11
Integral linearity ADS795XSB(2) –1 ±0.5 1 LSB(3)
ADS795XS(2) –1.5 ±0.75 1.5
Differential linearity ADS795XSB(2) –0.99 ±0.5 1 LSB
ADS795XS(2) –2 ±0.75 1.5
Offset error(4) –3.5 ±1.1 3.5 LSB
Gain error Range 1 –2 ±0.2 2 LSB
Range 2 ±0.2
Total unadjusted error (TUE) ±2 LSB
SAMPLING DYNAMICS
Conversion time 20 MHz SCLK 800 ns
Acquisition time 325 ns
Maximum throughput rate 20 MHz SCLK 1 MHz
Aperture delay 5 ns
Step response 150 ns
Overvoltage recovery 150 ns
DYNAMIC CHARACTERISTICS
Total harmonic distortion(5) 100 kHz –82 dB
Signal-to-noise ratio 100 kHz, ADS795XSB(2) 70 71.7 dB
100 kHz, ADS795XS(2) 70 71.7
Signal-to-noise + distortion 100 kHz, ADS795XSB(2) 69 71.3 dB
100 kHz, ADS795XS(2) 68 71.3
Spurious free dynamic range 100 kHz 84 dB
Small signal bandwidth At –3 dB 47 MHz
Channel-to-channel crosstalk Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input (isolation crosstalk). –95 dB
From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input (memory crosstalk). –85
EXTERNAL REFERENCE INPUT
VREF reference voltage at REFP(6) 2 2.5 3 V
Reference input resistance At fsample = 1 MHz 100 kΩ
ALARM SETTING
High threshold range 0 4092 LSB
Low threshold range 0 4092 LSB
DIGITAL INPUT/OUTPUT
Logic family CMOS
Logic level VIH 0.7*(+VBD) V
VIL +VBD = 5 V 0.8
VIL +VBD = 3 V 0.4
VOH At Isource = 200 μA +VBD-0.2
VOL At Isink = 200 μA 0.4
Data format MSB first MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage 2.7 3.3 5.25 V
+VBD supply voltage 1.7 3.3 5.25 V
Supply current (normal mode) At +VA = 2.7 to 3.6 V and 1 MHz throughput 1.8 mA
At +VA = 2.7 to 3.6 V static state 1.05
At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3
At +VA = 4.7 to 5.25 V static state 1.1 1.5
Power-down state supply current 1 μA
+VBD supply current +VA = 5.25 V, fs = 1MHz 1 mA
Power-up time 1 μs
Invalid conversions after power up or reset 1 Conversion
(1) Ideal input span; does not include gain or offset error.
(2) ADS795X, where X indicates 0, 1, 2, or 3.
(3) LSB means least significant bit.
(4) Measured relative to an ideal full-scale input.
(5) Calculated on the first nine harmonics of the input frequency.
(6) Device is designed to operate over VREF = 2 V to 3 V. However one can expect lower noise performance at Vref < 2.4 V. This is due to SNR degradation resulting from lowered signal range.

 
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