JAJS503C June 2008 – July 2018 ADS7950 , ADS7951 , ADS7952 , ADS7953 , ADS7954 , ADS7955 , ADS7956 , ADS7957 , ADS7958 , ADS7959 , ADS7960 , ADS7961
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUT | ||||||
Full-scale input span(1) | Range 1 | 0 | VREF | V | ||
Range 2 while 2xVREF ≤ +VA | 0 | 2*VREF | ||||
Absolute input range | Range 1 | –0.2 | VREF + 0.2 | V | ||
Range 2 while 2xVREF ≤ +VA | –0.2 | 2*VREF + 0.2 | ||||
Input capacitance | 15 | pF | ||||
Input leakage current | TA = 125°C | 61 | nA | |||
SYSTEM PERFORMANCE | ||||||
Resolution | 12 | Bits | ||||
No missing codes | ADS795XSB(2) | 12 | Bits | |||
ADS795XS(2) | 11 | |||||
Integral linearity | ADS795XSB(2) | –1 | ±0.5 | 1 | LSB(3) | |
ADS795XS(2) | –1.5 | ±0.75 | 1.5 | |||
Differential linearity | ADS795XSB(2) | –0.99 | ±0.5 | 1 | LSB | |
ADS795XS(2) | –2 | ±0.75 | 1.5 | |||
Offset error(4) | –3.5 | ±1.1 | 3.5 | LSB | ||
Gain error | Range 1 | –2 | ±0.2 | 2 | LSB | |
Range 2 | ±0.2 | |||||
Total unadjusted error (TUE) | ±2 | LSB | ||||
SAMPLING DYNAMICS | ||||||
Conversion time | 20 MHz SCLK | 800 | ns | |||
Acquisition time | 325 | ns | ||||
Maximum throughput rate | 20 MHz SCLK | 1 | MHz | |||
Aperture delay | 5 | ns | ||||
Step response | 150 | ns | ||||
Overvoltage recovery | 150 | ns | ||||
DYNAMIC CHARACTERISTICS | ||||||
Total harmonic distortion(5) | 100 kHz | –82 | dB | |||
Signal-to-noise ratio | 100 kHz, ADS795XSB(2) | 70 | 71.7 | dB | ||
100 kHz, ADS795XS(2) | 70 | 71.7 | ||||
Signal-to-noise + distortion | 100 kHz, ADS795XSB(2) | 69 | 71.3 | dB | ||
100 kHz, ADS795XS(2) | 68 | 71.3 | ||||
Spurious free dynamic range | 100 kHz | 84 | dB | |||
Small signal bandwidth | At –3 dB | 47 | MHz | |||
Channel-to-channel crosstalk | Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input (isolation crosstalk). | –95 | dB | |||
From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input (memory crosstalk). | –85 | |||||
EXTERNAL REFERENCE INPUT | ||||||
VREF reference voltage at REFP(6) | 2 | 2.5 | 3 | V | ||
Reference input resistance | At fsample = 1 MHz | 100 | kΩ | |||
ALARM SETTING | ||||||
High threshold range | 0 | 4092 | LSB | |||
Low threshold range | 0 | 4092 | LSB | |||
DIGITAL INPUT/OUTPUT | ||||||
Logic family | CMOS | |||||
Logic level | VIH | 0.7*(+VBD) | V | |||
VIL | +VBD = 5 V | 0.8 | ||||
VIL | +VBD = 3 V | 0.4 | ||||
VOH | At Isource = 200 μA | +VBD-0.2 | ||||
VOL | At Isink = 200 μA | 0.4 | ||||
Data format MSB first | MSB First | |||||
POWER SUPPLY REQUIREMENTS | ||||||
+VA supply voltage | 2.7 | 3.3 | 5.25 | V | ||
+VBD supply voltage | 1.7 | 3.3 | 5.25 | V | ||
Supply current (normal mode) | At +VA = 2.7 to 3.6 V and 1 MHz throughput | 1.8 | mA | |||
At +VA = 2.7 to 3.6 V static state | 1.05 | |||||
At +VA = 4.7 to 5.25 V and 1 MHz throughput | 2.3 | 3 | ||||
At +VA = 4.7 to 5.25 V static state | 1.1 | 1.5 | ||||
Power-down state supply current | 1 | μA | ||||
+VBD supply current | +VA = 5.25 V, fs = 1MHz | 1 | mA | |||
Power-up time | 1 | μs | ||||
Invalid conversions after power up or reset | 1 | Conversion |