JAJSBW2H November   2011  – June 2024 UCC27523 , UCC27525 , UCC27526

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 VDD and Undervoltage Lockout
      2. 7.3.2 Operating Supply Current
      3. 7.3.3 Input Stage
      4. 7.3.4 Enable Function
      5. 7.3.5 Output Stage
      6. 7.3.6 Low Propagation Delays and Tightly Matched Outputs
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input-to-Output Logic
        2. 8.2.2.2 Enable and Disable Function
        3. 8.2.2.3 VDD Bias Supply Voltage
        4. 8.2.2.4 Propagation Delay
        5. 8.2.2.5 Drive Current and Power Dissipation
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

VDD = 12 V, TA = TJ = –40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
BIAS CURRENTS
IDD(off) Start-up current,
 VDD = 3.4 V,
INA = VDD,
INB = VDD		 55 110 175 μA
VDD = 3.4 V,
INA = GND,
INB = GND		 25 75 145
UNDERVOLTAGE LOCKOUT (UVLO)
VON Supply start threshold TJ = 25°C 3.91 4.2 4.5 V
TJ = –40°C to 140°C 3.7 4.2 4.65
VOFF Minimum operating voltage after supply start 3.4 3.9 4.4
VDD_H Supply voltage hysteresis 0.2 0.3 0.5
INPUTS (INA, INB, INA+, INA–, INB+, INB–)
VIN_H Input signal high threshold Output high for non-inverting input pins
Output low for inverting input pins		 1.9 2.1 2.3 V
VIN_L Input signal low threshold Output low for non-inverting input pins
Output high for inverting input pins		 1 1.2 1.4
VIN_HYS Input hysteresis 0.7 0.9 1.1
ENABLE (ENA, ENB)
VEN_H Enable signal high threshold Output enabled 1.9 2.1 2.3 V
VEN_L Enable signal low threshold Output disabled 0.95 1.15 1.35
VEN_HYS Enable hysteresis 0.7 0.95 1.1
OUTPUTS (OUTA, OUTB)
ISNK/SRC Sink/source peak current(1) CLOAD = 0.22 µF, FSW = 1 kHz ±5 A
VDD-VOH High output voltage IOUT = –10 mA 0.075 V
VOL Low output voltage IOUT = 10 mA 0.01
ROH Output pullup resistance(2) IOUT = –10 mA 2.5 5 7.5 Ω
ROL Output pulldown resistance IOUT = 10 mA 0.15 0.5 1 Ω
(1) Ensured by design.
(2) ROH represents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC2752X output stage.