TPS1H100-Q1 40V、100mΩ、シングルチャネル、スマート・ハイサイド・パワー・スイッチ

1 特長

• 車載アプリケーション用に認定済み
• 下記内容でAEC-Q100認定済み:
  • デバイス温度グレード 1：動作時周囲温度範囲 –40°C～125°C
  • デバイス HBM ESD 分類レベル H3A
  • デバイス CDM ESD 分類レベル C4B
• 機能安全対応
  • 機能安全システムの設計に役立つ資料を利用可能
• 包括的な診断機能を備えたシングルチャネルのスマート・ハイサイド・パワー・スイッチ
  • バージョン A：オープン・ドレインのステータス出力
  • バージョン B：電流センス・アナログ出力
• 広い動作電圧範囲：3.5 ～ 40V
• 非常に低いスタンバイ電流：0.5µA 未満
• 動作時接合部温度範囲：–40～150°C
• 入力制御、3.3V および 5V ロジック互換
• 高精度電流センス：±30mA (1A 時)、±4mA (5mA 時)
  
• 外付け抵抗によるプログラマブル電流制限：±20% (0.5A 時)
• 診断イネーブル機能によって MCU のアナログ / デジタル・インターフェイスの多重化が可能
• AECQ100-12 グレード A に従ってテスト済み、
  100 万回の GND 短絡テスト
• 過渡電圧耐性に対する ISO7637-2 および ISO16750-2 の認定
• 保護
  • 過負荷および短絡保護
  • 誘導性負荷の負電圧クランプ
  • 低電圧誤動作防止 (UVLO) 保護
  • 自己回復可能なサーマル・シャットダウン / スイング
  • GND 喪失、電源喪失保護
  • 外部回路によるバッテリ逆極性保護
• 診断機能
  • オンおよびオフ状態での出力開放およびバッテリ短絡の検出
  • 過負荷およびグランド短絡検出、電流制限
  • サーマル・シャットダウン / スイング検出
• 熱特性強化型 14 ピン PWP パッケージ

2 アプリケーション

• サブモジュール用ハイサイド・パワー・スイッチ
• 低電力ランプ用パワー・スイッチ
• ハイサイド・リレーおよびソレノイド
• PLC デジタル出力パワー・スイッチ
• 一般的な抵抗性、誘導性、容量性負荷

3 概要

TPS1H100-Q1デバイスは各種の保護機能を搭載したハイサイド・パワー・スイッチで、NMOSパワーFETとチャージ・ポンプを内蔵して、抵抗性、誘導性、容量性の各種負荷をインテリジェントに制御することを目標にしています。高精度の電流センスとプログラマブル電流制限機能により、市場での差別化に役立ちます。

1. 提供されているすべてのパッケージについては、データシートの末尾にある注文情報を参照してください。

Device Images

代表的なアプリケーションの回路図

4 改訂履歴

Changes from C Revision (June 2018) to D Revision

• 「特長」セクションに機能安全対応のリンクを追加Go

Changes from B Revision (June 2015) to C Revision

• Changed the Pin Functions table to alphabetical order and created separate columns for the Version A and Version B devicesGo
• Added tablenotes to the Electrical Characteristics tableGo
• 「ドキュメントの更新通知を受け取る方法」セクションを追加Go

Changes from A Revision (January 2015) to B Revision

• Updated Figure 6 and Figure 7Go
• Updated Figure 38Go
• Updated Figure 39Go
• Updated Figure 40Go
• 「コミュニティ・リソース」を追加Go

Changes from * Revision (October 2014) to A Revision

• デバイス・ステータスをプレビューから量産データに更新Go

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

1. 4-layer board: FR4 2s2p board, 2.8-mil copper (top/bottom), 1.4-mil copper (internal layers). 76.4- × 114.3- × 1.5-mm board size.

2. 2-layer board: FR4 2s0p board, 2.8-mil copper (top/bottom). 76.4- × 114.3- × 1.5-mm board size.

Figure 1. R_θJA Value vs Copper Area

6.5 Electrical Characteristics

6.6 Timing Requirements – Current Sense Characteristics⁽¹⁾

Figure 2. CS Delay Characteristics

Figure 3. Open-Load Blanking Time Characteristics

Figure 4. Pin Current and Voltage Conventions

6.7 Switching Characteristics

Figure 5. Switching Characteristics Diagram

Figure 6. I_rev1 Test Condition

Figure 7. I_rev2 Test Condition

6.8 Typical Characteristics

Figure 8. V_VS,UVR and V_VS,UVF

Figure 10. I_off and I_leak,out

Figure 12. V_logic,h and V_logic,l

Figure 14. V_{DS, clamp}

Figure 16. I_lim,nom

Figure 18. dV/dtON and dV/dtOFF

Figure 20. V_ol,off

Figure 22. K_CS = 5 mA, 13.5 V

Figure 24. K_CS = 50 mA, 13.5 V

Figure 26. K_CS = 1 A, 13.5 V

Figure 28. K_CL = 1.6 A, 13.5 V

Figure 9. I_nom With No Load and 10-Ω Load

Figure 11. I_off,diag

Figure 13. VF

Figure 15. R_DSON

Figure 17. TDon and TDoff

Figure 19. V_CS,h

Figure 21. I_ol,on

Figure 23. K_CS = 25 mA, 13.5 V

Figure 25. K_CS = 100 mA, 13.5 V

Figure 27. K_CL = 0.5 A, 13.5 V

7 Detailed Description

7.1 Overview

The TPS1H100-Q1 is a single-channel, fully-protected, high-side power switch with an integrated NMOS power FET and charge pump. Full diagnostics and high-accuracy current-sense features enable intelligent control of the load. A programmable current-limit function greatly improves the reliability of the whole system. The device diagnostic reporting has two versions to support both digital status and analog current-sense output, both of which can be set to the high-impedance state when diagnostics are disabled, for multiplexing the MCU analog or digital interface among devices.

For version A, the digital status report is implemented with an open-drain structure. When a fault condition occurs, it pulls down to GND. A 3.3- or 5-V external pullup is required to match the microcontroller supply level. For version B, high-accuracy current sensing allows a better real-time monitoring effect and more-accurate diagnostics without further calibration. A current mirror is used to source 1 / K of the load current, which is reflected as voltage on the CS pin. K is a constant value across the temperature and supply voltage. The current-sensing function operates normally within a wide linear region from 0 to 4 V. The CS pin can also report a fault by pulling up the voltage of V_CS,h.

The external high-accuracy current limit allows setting the current limit value by application. It highly improves the reliability of the system by clamping the inrush current effectively under start-up or short-circuit conditions. Also, it can save system costs by reducing PCB trace, connector size, and the preceding power-stage capacity. An internal current limit is also implemented in this device. The lower value of the external or internal current-limit value is applied.

An active drain and source voltage clamp is built in to address switching off the energy of inductive loads, such as relays, solenoids, pumps, motors, and so forth. During the inductive switching-off cycle, both the energy of the power supply (E_BAT) and the load (E_LOAD) are dissipated on the high-side power switch itself. With the benefits of process technology and excellent IC layout, the TPS1H100-Q1 device can achieve excellent power dissipation capacity, which can help save the external free-wheeling circuitry in most cases. See Inductive-Load Switching-Off Clamp for more details.

Short-circuit reliability is critical for smart high-side power-switch devices. The standard of AEC-Q100-012 is to determine the reliability of the devices when operating in a continuous short-circuit condition. Different grade levels are specified according to the pass cycles. This device is qualified with the highest level, Grade A, 1 million times short-to-GND certification.

The TPS1H100-Q1 device can be used as a high-side power switch for a wide variety of resistive, inductive, and capacitive loads, including the low-wattage bulbs, LEDs, relays, solenoids, and heaters.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Accurate Current Sense

For version B, the high-accuracy current-sense function is internally implemented, which allows a better real-time monitoring effect and more-accurate diagnostics without further calibration. A current mirror is used to source 1 / K of the load current, flowing out to the external resistor between the CS pin and GND, and reflected as voltage on the CS pin.

K is the ratio of the output current and the sense current. It is a constant value across the temperature and supply voltage. Each device was internally calibrated while in production, so post-calibration by users is not required in most cases.

Figure 29. Current-Sense Accuracy

Ensure the CS voltage is in the linear region (0 to 4 V) during normal operation. Calculate R_CS with Equation 1.

Equation 1.

Also, when a fault condition occurs, CS works as a diagnostics report pin. When an open load or short to battery occurs in the on-state, V_CS almost equals 0. When current limit, thermal shutdown/swing, open load, or short to battery in the off-state occurs, the voltage is pulled up to V_CS,h. Figure 30 shows a typical current-sense voltage according to the operating conditions, including fault conditions.

Figure 30. Voltage Indication on the Current-Sense Pin

Figure 31. Current-Sense and Current-Limit Block Diagram

7.3.2 Programmable Current Limit

A high-accuracy current limit allows higher reliability, which protects the power supply during short circuit or power up. Also, it can save system costs by reducing PCB traces, connector size, and the capacity of the preceding power stage.

Current limit offers protection from overstressing to the load and integrated power FET. Current limit holds the current at the set value, and pulls up the CS pin to V_CS,h as a diagnostic report. The two current-limit thresholds are:

• External programmable current limit -- An external resistor is used to convert a proportional load current into a voltage, which is compared with an internal reference voltage, V_th,cl. When the voltage on the CL pin exceeds V_th.cl, a closed loop steps in immediately. V_GS voltage regulates accordingly, leading to the V_ds voltage regulation. When the closed loop is set up, the current is clamped at the set value. The external programmable current limit provides the capability to set the current-limit value by application.
• Internal current limit -- The internal current limit is fixed and typically 10 A. To use the internal current limit for large-current applications, tie the CL pin directly to the device GND.

Both the internal current limit (I_lim,nom) and external programmable current limit are always active when V_VS is powered and IN is high. The lower one (of I_lim,nom and the external programmable current limit) is applied as the actual current limit.

Note that if a GND network is used (which leads to the level shift between the device GND and board GND), the CL pin must be connected with device GND. Calculate R_CL with Equation 2.

Equation 2.

For better protection from a hard short-to-GND condition (when V_S and input are high and a short to GND happens suddenly), an open-loop fast-response behavior is set to turn off the channel, before the current-limit closed loop is set up. The open-loop response time is around 1 µs. With this fast response, the device can achieve better inrush-suppression performance.

7.3.3 Inductive-Load Switching-Off Clamp

When an inductive load is switching off, the output voltage is pulled down to negative, due to the inductance characteristics. The power FET may break down if the voltage is not clamped during the current-decay period. To protect the power FET in this situation, internally clamp the drain-to-source voltage, namely V_DS,clamp, the clamp diode between the drain and gate.

Equation 3.

During the current-decay period (T_DECAY), the power FET is turned on for inductance-energy dissipation. Both the energy of the power supply (E_BAT) and the load (E_LOAD) are dissipated on the high-side power switch itself, which is called E_HSD. If resistance is in series with inductance, some of the load energy is dissipated in the resistance.

Equation 4.

From the high-side power switch’s view, E_HSD equals the integration value during the current-decay period.

Equation 5.

Equation 6.

Equation 7.

When R approximately equals 0, E_HSD can be given simply as:

Equation 8.

Figure 32. Driving Inductive Load

Figure 33. Inductive-Load Switching-Off Diagram

As discussed previously, when switching off, battery energy and load energy are dissipated on the high-side power switch, which leads to the large thermal variation. For each high-side power switch, the upper limit of the maximum safe power dissipation depends on the device intrinsic capacity, ambient temperature, and board dissipation condition. TI provides the upper limit of single-pulse energy that devices can tolerate under the test condition: V_VS = 13.5 V, inductance from 0.1 mH to 400 mH, R = 0 Ω, FR4 2s2p board, 2- × 70-μm copper, 2- × 35-μm copper, thermal pad copper area 600 mm².

For one dedicated inductance, see Figure 34. If the maximum switching-off current is lower than the current value shown on the curve, the internal clamp function can be used for the demagnetization energy dissipation. If not, external free-wheeling circuitry is necessary for device protection.

Figure 34. Maximum Current vs Inductance Range

7.3.4 Full Protections and Diagnostics

Table 1 is when DIAG_EN enabled. When DIAG_EN is low, current sense or ST is disabled accordingly. The output is in high-impedance mode. Refer to Table 2 for details.

7.3.4.1 Short-to-GND and Overload Detection

In the on state, the short-to-GND fault is reported as the low status output or V_CS,h on CS, when a current limit is triggered. The lower one of the internal and external set values is applied for the actual current limit. It is in auto-recovery when the fault condition is cleared. If not cleared, thermal shutdown triggers to protect the power FET.

7.3.4.2 Open-Load Detection

In the on state for version A, if the current flowing through the output is less than I_ol,on, the device recognizes an open-load fault. For version B, faults are diagnosed by reading the voltage on the CS pin and judged by the user. A benefit of high-accuracy current sense down to a verylow current range, this device can achieve a very low open-load detection threshold, which correspondingly expands the normal operation region. TI suggests 10 mA as the upper limit for the open-load detection threshold and 25 mA as the lower limit for the normal operation current. In Figure 35, the recommended open-load detection region is shown as the dark-shaded region and the light-shaded region is for normal operation. As a guideline, do not overlap these two regions.

Figure 35. On-State Open-Load Detection and Normal-Operation Diagram

In the off state, if a load is connected, the output voltage is pulled to 0 V. In the case of an open load, the output voltage is close to the supply voltage, V_S – V_OUT < V_ol,off. For version A, the ST pin goes low to indicate the fault to the MCU. For version B, the CS pin is pulled up to V_CS,h. There is always a leakage current I_ol,off present on the output, due to the internal logic control path or external humidity, corrosion, and so forth. Thus, TI recommends an external pullup resistor to offset the leakage current. This pullup current should be less than the output load current to avoid false detection in the normal operation mode. To reduce the standby current, TI recommends always to use a switch in series with? the pullup resistor. TI recommends R_pu ≤ 15 kΩ.

Figure 36. Open-Load Detection Circuit

7.3.4.3 Short-to-Battery Detection

Short-to-battery detectioin has the same detection mechanism and behavior as open-load detection, both in the on-state and off-state. See the fault truth table, Table 1, for more details. In the on-state, the reverse current flows through the FET instead of the body diode, leading to less power dissipation. Thus, the worst case for off-state is when reverse current occurs. In the off-state, if V_OUT – V_VS < V_F, short to battery can be detected. (V_F is the body diode forward voltage and typically 0.7 V.) However, the reverse current does not occur. If V_OUT – V_VS > V_F, short to battery can be detected, and the reverse current should be lower than I_rev2 to ensure the survival of the device. TI recommends switching on the input for lower power dissipation or the reverse block circuitry for the supply. See Reverse Current Protection for more external protection circuitry information.

7.3.4.4 Reverse-Polarity Detection

Reverse-polarity detection has the same detection mechanism and behavior as open-load detection, both in the on-state and off-state. See the fault truth table, Table 1, for more details. In the on-state, the reverse current flows through the FET instead of the body diode, leading to less power dissipation. Thus, the worst case off-state is when reverse current occurs. In off-state, the reverse current should be lower than I_rev1 to ensure the survival of the device. See Reverse Current Protection for more external protection circuitry information.

7.3.4.5 Thermal Protection Behavior

Both the absolute temperature thermal shutdown and the dynamic temperature thermal swing diagnostic and protection are built into the device to increase the maximum reliability of the power FET. Thermal swing is active when the temperature of the power FET is increasing sharply, that is ΔT = T_DMOS – T_Logic > T_sw, then the output is shut down, and the ST pin goes low, or the CS pin is pulled up to V_CS,h. It auto-recovers and clears the fault signal until ΔT = T_DMOS – T_Logic < T_sw – T_hys. Thermal swing function improves device reliability against repetitive fast thermal variation, as shown in Figure 37. Multiple thermal swings are triggered before thermal shutdown happens. Thermal shutdown is active when absolute temperature T > T_SD. When active, the output is shut down, and the ST pin goes low, or the CS pin is pulled up to V_CS,h. The output is auto-recovered when T < T_SD – T_hys; the current limit is reduced to I_lim,tsd, or half of the programmable current limit value, to avoid repeated thermal shutdown. However, the thermal shutdown fault signal and half-current limit value are not cleared until the junction temperature decreases to less than T_SD,rst.

Figure 37. Thermal Behavior

7.3.4.6 UVLO Protection

The device monitors the supply voltage V_VS to prevent unpredicted behaviors in the event that the supply voltage is too low. When the supply voltage falls down to V_VS,UVF, the output stage is shut down automatically. When the supply rises up to V_VS,UVR, the device turns on.

7.3.4.7 Loss of GND Protection

When loss of GND occurs, output is turned off regardless of whether the input signal is high or low.

Case 1 (loss of device GND): Loss of GND protection is active when the Tab, I_{C_GND}, and current limit GND are one trace connected to the board GND, as shown in Figure 38. Tab floating is also a choice.

Figure 38. Loss of Device GND

Case 2 (loss of module GND): When the whole ECU module GND is lost, protections are also active. At this condition, the load GND remains connected.

Figure 39. Loss of Module GND

7.3.4.8 Loss of Power Supply Protection

When loss of supply occurs, output is turned off regardless of whether the input is high or low. For a resistive or capacitive load, loss-o-supply protection is easy to achieve due to no more power. The worst case is a charged inductive load. In this case, the current is driven from all of the IOs to maintain the inductance output loop. TI recommends either the MCU serial resistor plus the GND network (diode and resistor in parallel) or external free-wheeling circuitry.

Figure 40. Loss of Battery

7.3.4.9 Reverse Current Protection

Method 1: Block diode connected with V_S. Both the device and load are protected when in reverse polarity.

Figure 41. Reverse Protection With Block Diode

Method 2 (GND network protection): Only the high-side device is protected under this connection. The load reverse loop is limited by the load itself. Note when reverse polarity happens, the continuous reverse current through the power FET should be less than I_rev. Of the three types of ground pin networks, TI strongly recommends type 3 (the resistor and diode in parallel). No matter what types of connection are between the device GND and the board GND, if a GND voltage shift happens, ensure the following proper connections for the normal operation:

• Leave the NC pin floating or connect to the device GND. TI recommends to leave floating.
• Connect the current limit programmable resistor to the device GND.

Figure 42. Reverse Protection With GND Network

• Type 1 (resistor): The higher resistor value contributes to a better current limit effect when the reverse battery or negative ISO pulses. However, it leads to higher GND shift during normal operation mode. Also, consider the resistor’s power dissipation.
Equation 9.
Equation 10.
where
• V_GNDshift is the maximum value for the GND shift, determined by the HSD and microcontroller. TI suggests a value ≤ 0.6 V.
• I_nom is the nominal operating current.
• –V_CC is the maximum reverse voltage seen on the battery line.
• –I_GND is the maximum reverse current the ground pin can withstand, which is available in the Absolute Maximum Ratings.

If multiple high-side power switches are used, the resistor can be shared among devices.

• Type 2 (diode): A diode is needed to block the reverse voltage, which also brings a ground shift (≈ 600 mV). However, an inductive load is not acceptable to avoid an abnormal status when switching off.
• Type 3 (resistor and diode in parallel (recommended)): A peak negative spike may occur when the inductive load is switching off, which may damage the HSD or the diode. So, TI recommends a resistor in parallel with the diode when driving an inductive load. The recommended selection are 1-kΩ resistor in parallel with an I_F > 100-mA diode. If multiple high-side switches are used, the resistor and diode can be shared among devices.

7.3.4.10 Protection for MCU I/Os

In many conditions, such as the negative ISO pulse, or the loss of battery with an inductive load, a negative potential on the device GND pin may damage the MCU I/O pins [more likely, the internal circuitry connected to the pins]. Therefore, the serial resistors between MCU and HSD are required.

Also, for proper protection against loss of GND, TI recommends 4.7 kΩ when using 3.3-V MCU I/Os; 10 kΩ is for 5-V applications.

Figure 43. MCU IO Protections

7.3.5 Diagnostic Enable Function

The diagnostic enable pin, DIAG_EN, offers multiplexing of the microcontroller diagnostic input for current sense or digital status, by sharing the same sense resistor and ADC line or I/O port among multiple devices.

In addition, during the output-off period, the diagnostic disable function lowers the current consumption for the standby condition. The three working modes in the device are normal mode, standby mode, and standby mode with diagnostic. If off-state power saving is required in the system, the standby current is <500 nA with DIAG_EN low. If the off-state diagnostic is required in the system, the typical standby current is around 1 mA with DIAG_EN high.

7.4 Device Functional Modes

7.4.1 Working Mode

The three working modes in the device are normal mode, standby mode, and standby mode with diagnostic. If an off-state power saving is required in the system, the standby current is less than 500 nA with DIAG_EN low. If an off-state diagnostic is required in the system, the typical standby current is around 1 mA with DIAG_EN high. Note that to enter standby mode requires IN low and t > t_off,deg. t_off,deg is the standby-mode deglitch time, which is used to avoid false triggering. Figure 44 shows a work-mode state-machine state diagram.

Figure 44. Work-Mode State Machine

8 Application and Implementation

8.1 Application Information

The following discussion notes how to implement the device to distinguish the different fault modes and implement a ? transient-pulse immunity test.

In some applications, open load, short to battery, and short to GND must be distinguished from each other. This requires two steps.

8.2 Typical Application

Figure 45 shows an example of how to design the external circuitry parameters.

Figure 45. Typical Application Circuitry

8.2.1 Design Requirements

• V_S range from 9 V to 16 V
• Nominal current of 2 A
• Current sense for fault monitoring
• Expected current limit value of 5 A
• Full diagnostics with 5-V MCU
• Reverse protection with GND network

8.2.2 Detailed Design Procedure

The R_CS, V_CS linear region is from 0 to 4 V. To keep the 2-A nominal current in the 0- to 3-V range, calculate the R_CS as in Equation 11. To achieve better current sense accuracy, a 1% accuracy or better resistor is preferred.

Equation 11.

R_CL, V_CL,th is the current-limit internal threshold, 1.233 V. To set the programmable current limit value at 5 A, calculate the R_CL as in Equation 12.

Equation 12.

TI recommends R_SER = 10 kΩ for 5-V MCU.

TI recommends a 1-kΩ resistor and 200-V, 0.2-A diode for the GND network.

8.2.2.1 Distinguishing of Different Fault Modes

Some applications require that open load, short to battery, and short to GND can be distinguished from each other. This requires two steps:

1. In the on-state, for the current-sense version device (version B), on-state open load and short to battery are recognized as an extremely-low voltage level on the current-sense pin, whereas short to GND is reported as a pulled-up voltage V_CS,h. Therefore, the user can find a short to GND (see Figure 46).
2. If reported as an on-state open-load or short-to-battery fault in the first step, turn off the input signal. In the off-state, with an external pulldown resistor, open load and short to battery can be easily distinguished. When the output pulls down, the short to battery is still reported as an off-state fault condition, whereas the open load is ignored.

Figure 46. Step 1: Short-to-GND Detection in the On-State

Figure 47. Step 2: Short-to-Battery Detection in the Off-State

8.2.2.2 AEC Q100-012 Test Grade A Certification

Short-circuit reliability is critical for smart high-side power switch devices. The AEC-Q100-012 standard is used to determine the reliability of the devices when operating in a continuous short-circuit condition. Different grade levels are specified according to the pass cycles. This device is qualified with the highest level, Grade A, 1 million times short-to-GND certification.

Three test modes are defined in the AEC Q100-012 standard. See Table 3 for cold repetitive short-circuit test – long pulse, cold repetitive short-circuit test – short pulse, and hot repetitive short-circuit test.

Different grade levels are specified according to the pass cycles. The TPS1H100-Q1 device gets the certification of Grade A level, 1 million short-to-GND cycles, which is the highest test standard in the market.

8.2.2.3 EMC Transient Disturbances Test

Due to the severe electrical conditions in the automotive environment, immunity capacity against electrical transient disturbances is required, especially for a high-side power switch, which is connected directly to the battery. Detailed test requirements are in accordance with the ISO 7637-2:2011 and ISO 16750-2:2010 standards. The TPS1H100-Q1 device is tested and certificated by a third-party organization.

8.2.3 Application Curves

Figure 48 shows a test example of initial short-circuit inrush-current limit. Test conditions: V_S = 13.5 V, input is from low to high, load is short-to-GND or with a 470-µF capacitive load, external current limit is 2 A. CH1 is the output current. CH3 is the input step.

Figure 49 shows a test example of a hard short-circuit inrush-current limit. Test conditions: V_S= 13.5 V, input is high, load is 5 µH + 100 mΩ, external current limit is 1 A. A short to GND suddenly happens.

Figure 48. Initial Short-to-GND Waveform

Figure 49. Hard Short-to-GND Waveform

9 Power Supply Recommendations

10 Layout

10.1 Layout Guidelines

To prevent thermal shutdown, T_J must be less than 150°C. If the output current is very high, the power dissipation may be large. The HTSSOP package has good thermal impedance. However, the PCB layout is very important. Good PCB design can optimize heat transfer, which is absolutely essential for the long-term reliability of the device.

• Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-flow path from the package to the ambient is through the copper on the PCB. Maximum copper is extremely important when there are not any heat sinks attached to the PCB on the other side of the board opposite the package.
• Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board.
• All thermal vias should either be plated shut or plugged and capped on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.

10.2 Layout Example

10.2.1 Without a GND Network

Without a GND network, tie the thermal pad directly to the board GND copper for better thermal performance.

Figure 50. Layout Without a GND Network

10.2.2 With a GND Network

With a GND network, tie the thermal pad with a single trace through the GND network to the board GND copper.

Figure 51. Layout With a GND Network

10.3 Thermal Considerations

This device possesses thermal shutdown (TSD) circuitry as a protection from overheating. For continuous normal operation, the junction temperature should not exceed the thermal-shutdown trip point. If the junction temperature exceeds the thermal-shutdown trip point, the output turns off. When the junction temperature falls below the thermal-shutdown trip point, the output turns on again.

Calculate the power dissipated by the device according to Equation 13.

Equation 13.

where

• P_T = Total power dissipation of the device

After determining the power dissipated by the device, calculate the junction temperature from the ambient temperature and the device thermal impedance.

Equation 14.

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11.5 Glossary

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