JAJSC31E February   2014  – May 2018 TPS92630-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの回路図
  4. 4 改訂履歴
  5. 5 概要(続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Constant LED-Current Setting
      2. 9.3.2 PWM Control
      3. 9.3.3 FAULT Diagnostics
      4. 9.3.4 Short-Circuit Detection
      5. 9.3.5 Open-Load Detection
      6. 9.3.6 Thermal Foldback
    4. 9.4 Device Functional Modes
      1. 9.4.1 Thermal Information
      2. 9.4.2 Operation With V(VIN) < 5 V (Minimum V(VIN))
      3. 9.4.3 Operation With 5 V < V(VIN) < 9 V (Lower-Than-Normal Automotive Battery Voltage)
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Stoplight and Taillight Application With PWM Generator
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
          1. 10.2.1.2.1 Step-by-Step Design Procedure
            1. 10.2.1.2.1.1 R(REF)
            2. 10.2.1.2.1.2 Duty Cycle
            3. 10.2.1.2.1.3 Input and Output Capacitors
        3. 10.2.1.3 PWM Dimming Application Curve
      2. 10.2.2 Simple Stop-Light and Taillight Application
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
          1. 10.2.2.2.1 Step-by-Step Design Procedure
            1. 10.2.2.2.1.1 R(REF)
            2. 10.2.2.2.1.2 R(Stop)
            3. 10.2.2.2.1.3 Input and Output Capacitors
      3. 10.2.3 Parallel Connection
        1. 10.2.3.1 Design Requirements
        2. 10.2.3.2 Detailed Design Procedure
          1. 10.2.3.2.1 Step-by-Step Design Procedure
            1. 10.2.3.2.1.1 R(REF)
            2. 10.2.3.2.1.2 Input and Output Capacitors
      4. 10.2.4 Alternate Parallel Connection
        1. 10.2.4.1 Design Requirements
        2. 10.2.4.2 Detailed Design Procedure
          1. 10.2.4.2.1 Step-by-Step Design Procedure
            1. 10.2.4.2.1.1 R(REF)
            2. 10.2.4.2.1.2 Input and Output Capacitors
      5. 10.2.5 High-Side PWM Dimming
        1. 10.2.5.1 Design Requirements
        2. 10.2.5.2 Detailed Design Procedure
          1. 10.2.5.2.1 Step-by-Step Design Procedure
            1. 10.2.5.2.1.1 Ratio of Resistors, R1 / R2
            2. 10.2.5.2.1.2 R1 and R2 Selection
            3. 10.2.5.2.1.3 Input and Output Capacitors
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 ドキュメントの更新通知を受け取る方法
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

7.5 Electrical Characteristics

V(VIN) = 14 V, TJ = –40°C to 150°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE AND CURRENT (VIN)
VI Input voltage 5 40 V
I(quiescent) Quiescent current All PWMx = high, I(IOUTx) = 100 mA,
Not including Iref 		0.5 0.6 0.85 mA
IO(sd) Shutdown current V(EN) = 0 V 10 µA
I(fault) Shutdown current in fault mode (device to GND) PWM = EN = high, FAULT = low, V(VIN) = 5 V–40 V, I = 100 mA 0.5 0.6 0.85 mA
Shutdown current in fault mode (from V(VIN)) PWM = EN = high, FAULT = low, V(VIN) = 5 V–40 V, I = 100 mA 2
PWMx AND EN
VIL(EN) Logic input, low level IOUTx disabled   0 0.7 V
VIH(EN) Logic input, high level IOUTx enabled  2 V
I(EN-pd) EN internal pulldown V(EN) = 0 V to 40 V 0.35 5 µA
VIL(PWMx) Logic input, low level IOUTx disabled 1.135 1.195 1.255 V
VIH(PWMx) Logic input, high level IOUTx enabled 1.161 1.222 1.283 V
Vhys(PWM) Hysteresis 44 mV
I(PWM-pd) PWMx internal pulldown current V(PWMx) = 40 V 100 180 250 nA
CURRENT REGULATION (IOUTx)
I(IOUTx) Regulated output current range Each channel 10 150 mA
Three channels in parallel mode 30 450
ΔIO(channel) Channel accuracy 10 mA < I(IOUTx) < 30 mA, V(VIN) = 5 V–40 V
TPS92630-Q1 Inl1_ChaAcc_slvsc76.gif(1) 		–3% 3%
30 mA ≤ I(IOUTx) < 150 mA, Vin = 5 V–40 V
TPS92630-Q1 Inl1_ChaAcc_slvsc76.gif(1) 		–1.5% 1.5%
ΔIO(device) Device accuracy 10 mA < I(IOUTx) < 30 mA, V(VIN) = 5 V to 20 V(2)
TPS92630-Q1 Inl2_DevAcc_slvsc76.gif(3) 		–4% 4%
30 mA ≤ IOUT < 150 mA, V(VIN) = 5 V to 20 V(2)
TPS92630-Q1 Inl2_DevAcc_slvsc76.gif(3) 		–2.5% 2.5%
Vref Reference voltage 1.198 1.222 1.246 V
K(I) Ratio of I(IOUTx) to reference current 100
V(DROP) Dropout voltage At 150 mA load per channel 0.6 0.9 V
At 60 mA load per channel 0.24 0.4
SR Current rise and fall slew rates Current rising from 10% to 90% or falling from 90% to 10% at I(IOUTx) = 60 mA.(4) 4 8 15 mA/µs
Current rising from 10% to 90% or falling from 90% to 10% at I(IOUTx) = 150 mA.(4) 7 14 25 mA/µs
FAULT (FAULT)
VIL Logic input low threshold 0.7 V
VIH Logic input high threshold 2 V
VOL Logic output low level Tested with 500-µA external pullup 0.7 V
VOH Logic output high level Tested with 1-µA external pulldown  2 V
I(pulldown) Strong pulldown current 500 750 1000 µA
I(pullup) Weak pullup current 4 8 16 µA
COMPARATOR (VSNSx)
V(VSNSx) Internal comparator reference (for short circuit detection) V(VIN) > V(th) 1.198 1.222 1.246 V
Ilkg Leakage current V(VSNSx) = 3 V 500 nA
V(th) Voltage at which the chip enables the single-short alarm function Single-short detection enabled 8 9 V
V(th) hysteresis 145 mV
PROTECTION
V(OLV) Open-load detection voltage V(OLV) = V(VIN) – V(IOUTx) 50 100 150 mV
V(OL-hys) Open-load detection hysteresis 100 200 300 mV
V(SV) Short-detection voltage 0.846 0.89 0.935 V
Short-detection hysteresis 318 335 352 mV
Short-detection deglitch 1 2 3 ms
During PWM, count the number of continuous cycles when V(IOUTx) < V(SV) 7 8 Cycles
R(REF_open) REF pin resistor open detection FAULT goes low 15 23 57 kΩ
R(REF_short) REF pin resistor short detection FAULT goes low 350 470 800 Ω
THERMAL MONITOR
T(shutdown) Thermal shutdown 155 170 170 °C
T(hys) Thermal shutdown hysteresis 15 °C
T(th) Thermal foldback activation temperature 90% of I(IOUTx) normal (TEMP pin floating) 95 110 125 °C
I(TFCmin) Minimum foldback current 40% 50% 60%
V(T-disable) Thermal-foldback-function disable voltage 0 0.2 V
(1) I(AVG) = [I(IOUT1) + I(IOUT2) + I(IOUT3)] / 3
(2) For V(VIN) voltages higher than 20 V, see Figure 2 and Figure 3.
(3) I(setting) is the target current set by Rref.
(4) See Figure 17 for the load model for the slew-rate test and delay-time test.