JAJSC60F April   2016  – June 2024 THS6212

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics VS = 12 V
    6. 5.6 Electrical Characteristics VS = 28 V
    7. 5.7 Timing Requirements
    8. 5.8 Typical Characteristics: VS = 12 V
    9. 5.9 Typical Characteristics: VS = 28 V
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Voltage and Current Drive
      2. 6.3.2 Driving Capacitive Loads
      3. 6.3.3 Distortion Performance
      4. 6.3.4 Differential Noise Performance
      5. 6.3.5 DC Accuracy and Offset Control
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Wideband Current-Feedback Operation
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 Dual-Supply Downstream Driver
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
          1. 7.2.2.2.1 Line Driver Headroom Requirements
          2. 7.2.2.2.2 Computing Total Driver Power for Line-Driving Applications
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.8 Typical Characteristics: VS = 12 V

at TA ≅ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode (unless otherwise noted)

THS6212 Small-Signal Frequency Response
VO = 2 VPP
Figure 5-1 Small-Signal Frequency Response
THS6212 Out-of-Band Suppression
SGCC HPLC profiles, crest factor = 5 V/V
Figure 5-3 Out-of-Band Suppression
THS6212 Small-Signal Frequency Response vs RF
AV = 10 V/V, VO = 2 VPP
Figure 5-5 Small-Signal Frequency Response vs RF
THS6212 Small-Signal Gain Flatness vs RF
AV = 10 V/V, VO = 2 VPP
Figure 5-7 Small-Signal Gain Flatness vs RF
THS6212 Large-Signal Gain Flatness
VO = 16 VPP
 
 
Figure 5-9 Large-Signal Gain Flatness
THS6212 Large-Signal Frequency Response vs VO
AV = 10 V/V
Figure 5-11 Large-Signal Frequency Response vs VO
THS6212 Small-Signal Frequency Response vs Bias Modes
AV = 10 V/V, VO = 2 VPP
Figure 5-13 Small-Signal Frequency Response vs Bias Modes
THS6212 Large-Signal Frequency Response vs Bias Modes
AV = 15 V/V, VO = 16 VPP
Figure 5-15 Large-Signal Frequency Response vs Bias Modes
THS6212 Harmonic Distortion vs Frequency
VO = 2 VPP
Figure 5-17 Harmonic Distortion vs Frequency
THS6212 Harmonic Distortion vs VO
f = 1 MHz, AV = 10 V/V
Figure 5-19 Harmonic Distortion vs VO
THS6212 Harmonic Distortion vs RL
f = 1 MHz, VO = 2 VPP, AV = 10 V/V
Figure 5-21 Harmonic Distortion vs RL
THS6212 Intermodulation Distortion vs Frequency
±12.2 kHz tone spacing, VO = 2 VPP per tone
Figure 5-23 Intermodulation Distortion vs Frequency
THS6212 Small-Signal Pulse Response
VO step = 2 VPP
Figure 5-25 Small-Signal Pulse Response
THS6212 Open-Loop Transimpedance Gain and Phase vs Frequency
Full-bias simulation
Figure 5-27 Open-Loop Transimpedance Gain and Phase vs Frequency
THS6212 Open-Loop Transimpedance Gain and Phase vs Frequency
Low-bias simulation
Figure 5-29 Open-Loop Transimpedance Gain and Phase vs Frequency
THS6212 Quiescent Current vs Single-Supply Voltage
RL = no load
Figure 5-31 Quiescent Current vs Single-Supply Voltage
THS6212 Quiescent Current vs Temperature
RL = no load
Figure 5-33 Quiescent Current vs Temperature
THS6212 Mode Transition Voltage Threshold
B1 = full-bias to mid-bias transition with B2 = GND pin,
B2 = full-bias to low-bias transition with B1 = GND pin,
GND pin = VS–
Figure 5-35 Mode Transition Voltage Threshold
THS6212 Large-Signal Frequency Response
VO = 16 VPP
Figure 5-2 Large-Signal Frequency Response
THS6212 Small-Signal Frequency Response vs Temperature
AV = 15 V/V, VO = 2 VPP
Figure 5-4 Small-Signal Frequency Response vs Temperature
THS6212 Small-Signal Frequency Response vs RF
AV = 15 V/V, VO = 2 VPP
Figure 5-6 Small-Signal Frequency Response vs RF
THS6212 Small-Signal Gain Flatness vs RF
AV = 15 V/V, VO = 2 VPP
Figure 5-8 Small-Signal Gain Flatness vs RF
THS6212 Small-Signal Frequency Response vs CLOAD
VO = 100 mVPP
Frequency response is measured at the device output pin before the isolation resistor.
Figure 5-10 Small-Signal Frequency Response vs CLOAD
THS6212 Large-Signal Frequency Response vs VO
AV = 15 V/V
Figure 5-12 Large-Signal Frequency Response vs VO
THS6212 Small-Signal Frequency Response vs Bias Modes
AV = 15 V/V, VO = 2 VPP
Figure 5-14 Small-Signal Frequency Response vs Bias Modes
THS6212 Input Voltage and Current Noise Density vs Frequency
Figure 5-16 Input Voltage and Current Noise Density vs Frequency
THS6212 Harmonic Distortion vs Gain
f = 1 MHz, VO = 2 VPP
Figure 5-18 Harmonic Distortion vs Gain
THS6212 Harmonic Distortion vs VO
f = 10 MHz, AV = 10 V/V
Figure 5-20 Harmonic Distortion vs VO
THS6212 Harmonic Distortion vs RL
f = 10 MHz, VO = 2 VPP, AV = 10 V/V
Figure 5-22 Harmonic Distortion vs RL
THS6212 Overdrive Recovery
VIN = 2.8-VPP triangular waveform
Figure 5-24 Overdrive Recovery
THS6212 Large-Signal Pulse Response
VO step = 16 VPP
Figure 5-26 Large-Signal Pulse Response
THS6212 Open-Loop Transimpedance Gain and Phase vs Frequency
Mid-bias simulation
Figure 5-28 Open-Loop Transimpedance Gain and Phase vs Frequency
THS6212 Open-Loop Output Impedance vs Frequency
Simulation
Figure 5-30 Open-Loop Output Impedance vs Frequency
THS6212 Quiescent Current vs RADJ
RL = no load
Figure 5-32 Quiescent Current vs RADJ
THS6212 PSRR and CMRR vs Frequency
TJ = 50°C, simulation
Figure 5-34 PSRR and CMRR vs Frequency
THS6212 Full-Bias and Shutdown Mode Transition Timing
 
 
 
Figure 5-36 Full-Bias and Shutdown Mode Transition Timing