JAJSCB5B May 2016 – September 2017 TPS22975
PRODUCTION DATA.
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 ON and OFF Control
The ON pin controls the state of the switch. ON is active high and has a 1.2-V ON-pin enable threshold, making it capable of interfacing with low-voltage signals. The ON pin is compatible with standard GPIO logic thresholds. It can be used with any microcontroller with 1.2 V or higher GPIO voltage. This pin cannot be left floating and must be driven either high or low for proper functionality.
10.1.2 Input Capacitor (CIN) (Optional)
To limit the voltage drop on the input supply caused by transient inrush currents when the switch turns on into a discharged load capacitor or short-circuit, a capacitor needs to be placed between VIN and GND. A 1-µF ceramic capacitor, CIN, placed close to the pins, is usually sufficient. Higher values of CIN can be used to further reduce the voltage drop during high current applications. When switching heavy loads, it is recommended to have an input capacitor about 10 times higher than the output capacitor (CL) to avoid excessive voltage drop.
10.1.3 Output Capacitor (CL) (Optional)
Because of the integrated body diode in the NMOS switch, a CIN greater than CL is highly recommended. A CL greater than CIN can cause VOUT to exceed VIN when the system supply is removed. This could result in current flow through the body diode from VOUT to VIN. A CIN to CL ratio of 10 to 1 is recommended for minimizing VIN dip caused by inrush currents during startup; however, a 10 to 1 ratio for capacitance is not required for proper functionality of the device. A ratio smaller than 10 to 1 (such as 1 to 1) could cause slightly more VIN dip upon turn-on because of inrush currents. This can be mitigated by increasing the capacitance on the CT pin for a longer rise time (see the Adjustable Rise Time section).
10.2 Typical Application
For optimal RON performance, it is recommended to have VIN ≤ VBIAS. The device is functional if VIN > VBIAS but it exhibits RON greater than what is listed in the Electrical Characteristics—VBIAS = 5 V and Electrical Characteristics—VBIAS = 2.5 V tables.
Figure 31 demonstrates how the TPS22975 can be used to power downstream modules.
Figure 31. Powering a Downstream Module
10.2.1 Design Requirements
| DESIGN PARAMETER | EXAMPLE VALUE |
|---|---|
| VIN | 3.3 V |
| VBIAS | 5 V |
| CL | 22 µF |
| Maximum Acceptable Inrush Current | 400 mA |
10.2.2 Detailed Design Procedure
10.2.2.1 Inrush Current
When the switch is enabled, the output capacitors must be charged up from 0 V to the set value (3.3 V in this example). This charge arrives in the form of inrush current. Inrush current can be calculated using Equation 2.
where
- CL is the output capacitance
- dVOUT is the change in VOUT during the ramp up of the output voltage when device is enabled.
- dt is the rise time in VOUT during the ramp up of the output voltage when the device is enabled.
The TPS22975 offers adjustable rise time for VOUT. This feature allows the user to control the inrush current during turnon. The appropriate rise time can be calculated using the design requirements and the inrush current equation as shown in Equation 3.
The value of dt is given by Equation 4.
To ensure an inrush current of less than 400 mA, choose a CT value that yields a rise time of more than 181.5 µs. See the oscilloscope captures in the Application Curves section for an example of how the CT capacitor can be used to reduce inrush current.
10.2.3 Application Curves
| VBIAS = 5 V | VIN = 3.3 V | CL = 22 µF |
| VBIAS = 5 V | VIN = 3.3 V | CL = 22 µF |