JAJSCC4A July   2016  – January 2024 DS90UB964-Q1

PRODUCTION DATA  

  1.   1
  2. 1特長
  3. 2アプリケーション
  4. 3概要
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings – JEDEC
    3. 4.3  ESD Ratings – IEC and ISO
    4. 4.4  Recommended Operating Conditions
    5. 4.5  Thermal Information
    6. 4.6  DC Electrical Characteristics
    7. 4.7  AC Electrical Characteristics
    8. 4.8  Recommended Timing for the Serial Control Bus
    9. 4.9  AC Electrical Characteristics
    10. 4.10 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
      1. 5.1.1 Functional Description
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1  RAW Data Type Support and Rates
      2. 5.4.2  MODE Pin
      3. 5.4.3  REFCLK
      4. 5.4.4  Receiver Port Control
      5. 5.4.5  Input Jitter Tolerance
      6. 5.4.6  Adaptive Equalizer
        1. 5.4.6.1 Channel Requirements
        2. 5.4.6.2 Adaptive Equalizer Algorithm
        3. 5.4.6.3 AEQ Settings
          1. 5.4.6.3.1 AEQ Start-Up and Initialization
          2. 5.4.6.3.2 AEQ Range
          3. 5.4.6.3.3 AEQ Timing
          4. 5.4.6.3.4 AEQ Threshold
      7. 5.4.7  Channel Monitor Loop-Through Output Driver
        1. 5.4.7.1 Code Example for CMLOUT FPD3 RX Port 0:
      8. 5.4.8  RX Port Status
        1. 5.4.8.1 RX Parity Status
        2. 5.4.8.2 FPD-Link Decoder Status
        3. 5.4.8.3 RX Port Input Signal Detection
      9. 5.4.9  GPIO Support
        1. 5.4.9.1 GPIO Input Control and Status
        2. 5.4.9.2 GPIO Output Pin Control
        3. 5.4.9.3 Back Channel GPIO
        4. 5.4.9.4 GPIO Pin Status
        5. 5.4.9.5 Other GPIO Pin Controls
      10. 5.4.10 RAW Mode LV / FV Controls
      11. 5.4.11 Video Stream Forwarding
      12. 5.4.12 CSI-2 Protocol Layer
      13. 5.4.13 CSI-2 Short Packet
      14. 5.4.14 CSI-2 Long Packet
      15. 5.4.15 CSI-2 Data Identifier
      16. 5.4.16 Virtual Channel and Context
      17. 5.4.17 CSI-2 Mode Virtual Channel Mapping
        1. 5.4.17.1 Example 1
        2. 5.4.17.2 Example 2
      18. 5.4.18 CSI-2 Transmitter Frequency
      19. 5.4.19 CSI-2 Transmitter Status
      20. 5.4.20 Video Buffers
      21. 5.4.21 CSI-2 Line Count and Line Length
      22. 5.4.22 FrameSync Operation
        1. 5.4.22.1 External FrameSync Control
        2. 5.4.22.2 Internally Generated FrameSync
          1. 5.4.22.2.1 Code Example for Internally Generated FrameSync
      23. 5.4.23 CSI-2 Forwarding
        1. 5.4.23.1 Best-Effort Round Robin CSI-2 Forwarding
        2. 5.4.23.2 Synchronized CSI-2 Forwarding
        3. 5.4.23.3 Basic Synchronized CSI-2 Forwarding
          1. 5.4.23.3.1 Code Example for Basic Synchronized CSI-2 Forwarding
        4. 5.4.23.4 Line-Interleaved CSI-2 Forwarding
          1. 5.4.23.4.1 Code Example for Line-Interleaved CSI-2 Forwarding
        5. 5.4.23.5 Line-Concatenated CSI-2 Forwarding
          1. 5.4.23.5.1 Code Example for Line-Concatenated CSI-2 Forwarding
        6. 5.4.23.6 CSI-2 Replicate Mode
        7. 5.4.23.7 CSI-2 Transmitter Output Control
        8. 5.4.23.8 Enabling and Disabling CSI-2 Transmitters
    5. 5.5 Programming
      1. 5.5.1  Serial Control Bus
      2. 5.5.2  Second I2C Port
      3. 5.5.3  I2C Target Operation
      4. 5.5.4  Remote Target Operation
      5. 5.5.5  Remote Target Addressing
      6. 5.5.6  Broadcast Write to Remote Devices
        1. 5.5.6.1 Code Example for Broadcast Write
      7. 5.5.7  I2C Proxy Controller
      8. 5.5.8  I2C Proxy Controller Timing
        1. 5.5.8.1 Code Example for Configuring Fast-Mode Plus I2C Operation
      9. 5.5.9  Interrupt Support
        1. 5.5.9.1 Code Example to Enable Interrupts
        2. 5.5.9.2 FPD-Link III Receive Port Interrupts
        3. 5.5.9.3 Code Example to Readback Interrupts
        4. 5.5.9.4 CSI-2 Transmit Port Interrupts
      10. 5.5.10 Timestamp – Video Skew Detection
      11. 5.5.11 Pattern Generation
        1. 5.5.11.1 Reference Color Bar Pattern
        2. 5.5.11.2 Fixed Color Patterns
        3. 5.5.11.3 Pattern Generator Programming
          1. 5.5.11.3.1 Determining Color Bar Size
        4. 5.5.11.4 Code Example for Pattern Generator
      12. 5.5.12 FPD-Link BIST Mode
        1. 5.5.12.1 BIST Operation
    6. 5.6 Register Maps
      1. 5.6.1 Main_Page Registers
      2. 5.6.2 Indirect Access Registers
        1. 5.6.2.1 PATGEN_And_CSI-2 Registers
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power-Over-Coax
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
      3. 6.2.3 Application Curves
    3. 6.3 System Examples
    4. 6.4 Power Supply Recommendations
      1. 6.4.1 VDD Power Supply
      2. 6.4.2 Power-Up Sequencing
        1. 6.4.2.1 PDB Pin
    5. 6.5 Layout
      1. 6.5.1 Layout Guidelines
        1. 6.5.1.1 Ground
        2. 6.5.1.2 Routing FPD-Link III Signal Traces and PoC Filter
        3. 6.5.1.3 CSI-2 Guidelines
      2. 6.5.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 サポート・リソース
    4. 7.4 Trademarks
    5. 7.5 静電気放電に関する注意事項
    6. 7.6 用語集
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

Pin Configuration and Functions

GUID-20231023-SS0I-GMXM-B9VV-MTJV6N9KGTZJ-low.svg Figure 4-1 RGC Package
64 Pin VQFN
(Top View)
Table 4-1 Pin Functions
PIN I/O
TYPE		 DESCRIPTION
NAME NO.
MIPI CSI-2 TX INTERFACE
CSI0_CLKN 22 O CSI-2 TX Port 0 differential clock output pins.
Leave unused pins as No Connect.
CSI0_CLKP 23
CSI0_D0N 24 CSI-2 TX Port 0 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control.
Leave unused pins as No Connect.
CSI0_D0P 25
CSI0_D1N 26
CSI0_D1P 27
CSI0_D2N 28
CSI0_D2P 29
CSI0_D3N 30
CSI0_D3P 31
CSI1_CLKN 34 O CSI-2 TX Port 1 differential clock output pins.
Leave unused pins as No Connect.
CSI1_CLKP 35
CSI1_D0N 36 CSI-2 TX Port 1 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control.
Leave unused pins as No Connect.
CSI1_D0P 37
CSI1_D1N 38
CSI1_D1P 39
CSI1_D2N 40
CSI1_D2P 41
CSI1_D3N 42
CSI1_D3P 43
FPD-LINK III RX INTERFACE
RIN0+ 50 I/O FPD-Link III RX Port 0 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 0 to 0 to disable RX Port 0 and leave the pins as No Connect.
RIN0- 51
RIN1+ 53 FPD-Link III RX Port 1 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 1 to 0 to disable RX Port 1 and leave the pins as No Connect.
RIN1- 54
RIN2+ 59 FPD-Link III RX Port 2 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 2 to 0 to disable RX Port 2 and leave the pins as No Connect.
RIN2- 60
RIN3+ 62 FPD-Link III RX Port 3 pins. The port receives FPD-Link III high-speed forward channel video and control data and transmits back channel control data. The port can interface with a compatible FPD-Link III serializer TX through an STP or coaxial cable (see Figure 6-3 and Figure 6-4). The port must be AC-coupled per Table 6-3.
If port is unused, set RX_PORT_CTL register bit 3 to 0 to disable RX Port 3 and leave the pins as No Connect.
RIN3- 63
GENERAL-PURPOSE I/O
GPIO0 9 I/O, PD General-Purpose Input/Output pins. The pins can be used to control and respond to various commands. The pins can be configured to be input signals for the corresponding GPIOs on the serializer, or the pins can be configured to be outputs to follow local register settings. At power up, the GPIO pins are disabled and by default include a pulldown resistor (25kΩ typical).
See Section 5.4.9. for programmability. If unused, leave the pin as No Connect.
GPIO1 10
GPIO2 14
GPIO3 15
GPIO4 17
GPIO5 18
GPIO6 19
GPIO7 20
SERIAL CONTROL BUS (I2C)
I2C_SCL 12 I/O, OD Primary I2C Clock Input / Output interface pin. See Section 5.5.1.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
I2C_SDA 11 I/O, OD Primary I2C Data Input / Output interface pin. See Section 5.5.1.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
I2C_SCL2 8 I/O, OD Secondary I2C Clock Input / Output interface pin. See Section 5.5.2.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
I2C_SDA2 7 I/O, OD Secondary I2C Data Input / Output interface pin. See Section 5.5.2.
Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO.
CONFIGURATION AND CONTROL
IDX 46 S I2C Serial Control Bus Device ID Address Select configuration pin.
Connect to an external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 5-13.
MODE 45 S Mode Select configuration pin.
Connect to external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 5-2.
PDB 3 I, PD Inverted Power-Down input pin. Typically connected to a processor GPIO with a pulldown. When PDB input is brought HIGH, the device is enabled and internal registers and state machines are reset to default values. Asserting PDB signal low powers down the device and consumes minimum power. The default function of this pin is PDB = LOW; POWER DOWN with an internal 50kΩ internal pulldown enabled. PDB must remain low until after power supplies are applied and reach minimum required levels. See Section 6.4.1.
INPUT IS 3.3V TOLERANT
PDB = 1.8V or 3.3V, device is enabled (normal operation)
PDB = 0V, device is powered down.
POWER AND GROUND
VDDIO 16 P 1.8V (±5%) OR 3.3V (±10%) LVCMOS I/O Power
Recommend 1μF, 0.1F, and 0.1μF or 0.01μF capacitors to GND (see Section 6.2)
VDD_CSI0
VDD_CSI1		 21
33		 P 1.1V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 1μF decoupling is recommended for the pin group (see Section 6.2)
VDDL1
VDDL2		 13
44		 P 1.1V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD_FPD1
VDD_FPD2		 52
61		 P 1.1V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD18_P2
VDD18_P3
VDD18_P1
VDD18_P0		 2
1
47
48		 P 1.8V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD18A 32 P 1.8V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF, and 1μF decoupling is recommended for the pin group (see Section 6.2)
VDD18_FPD0
VDD18_FPD1
VDD18_FPD2
VDD18_FPD3		 49
55
58
64		 P 1.8V (±5%) Power Supplies
Recommend 0.1μF or 0.01μF capacitors to GND at each VDD pin. Additional 0.1μF, 1μF, and 10uF decoupling is recommended for the pin group (see Section 6.2)
GND DAP G DAP is the large metal contact at the bottom side, located at the center of the VQFN package. Connect to the ground plane (GND).
OTHERS
INTB 6 O, OD Interrupt Output pin.
INTB is an active-low open drain and controlled by the status registers. See Section 5.5.9.
Recommend a 4.7kΩ Pullup to 1.8V or 3.3V. If unused, leave the pin as No Connect.
REFCLK 5 I Reference clock oscillator input.
Typically connected to a 23MHz to 25MHz LVCMOS-level oscillator (100 ppm).
For 400Mbps, 800Mbps or 1.6Gbps CSI-2 data rates, use 25MHz frequency. For <1.5Gbps operation use 23MHz (1.47Gbps)
For the oscillator requirements, see Section 5.4.3. For other common CSI-2 data rates, see Section 5.4.18.
RES 4 - This pin must be tied to GND for normal operation.
CMLOUTP 56 O Channel Monitor Loop-through Driver differential output.
Route to a test point or a pad with 100Ω termination resistor between pins for channel monitoring (recommended). See Section 5.4.7.
CMLOUTN 57
The definitions below define the functionality of the I/O cells for each pin. TYPE:
  • I = Input
  • O = Output
  • I/O = Input/Output
  • S = Strap Input
  • PD = Internal Pulldown
  • OD = Open Drain
  • P = Power Supply
  • G = Ground